FPGA implementation of a cholesky algorithm for a shared-memory multiprocessor architecture

Parallel Algorithms and Applications

Volumn 19, Issue 4, 2004, Pages 211-226

  Haridas, Satchidanand G ^a   Ziavras, Sotirios G ^a  

^a NEW JERSEY INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

FPGA; Matrix inversion; Parallel Cholesky factorization; Performance evaluation

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; INVERSE PROBLEMS; LINEAR EQUATIONS; MATHEMATICAL OPERATORS; MATRIX ALGEBRA; PARALLEL PROCESSING SYSTEMS; ROUTERS;

MATRIX FACTORIZATION; MATRIX INVERSION; PARALLEL CHOLESKY FACTORIZATION; PERFORMANCE EVALUATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 6344242990     PISSN: 10637192     EISSN: None     Source Type: Journal    
DOI: 10.1080/10637190412331279957     Document Type: Article

References (17)

1. Altera Corp. (2002) Nios 2.0 CPU Data Sheet, Altera Data Sheet DS-NIOSCPU-1.0 (Altera Corporation, San Jose, CA).
2. Altera Corp. (2001) System-on-a-Programmable Chip Development Board User Guide, Altera Document A-UG-SOPC-1.3, (Altera Corporation, San Jose, CA).
3. Brown, S. and Rose, J. (1996) "Architecture of FPGAs and CPLDs: a tutorial", IEEE Des. Test Comput. 13.2, 42-57.
4. Demmel, J.W., et al. (1999) "A supernodal approach to sparse partial pivoting", SIAM J. Matrix Anal. Appl. 20.3, 720-755.
5. Gallivan, K.A., et al. (1990) Parallel Algorithms for Matrix Computations (SIAM, Philadelphia, PA).
6. George, A., Heath, M.T. and Liu, J. (1986) "Parallel Cholesky factorization on shared-memory multiprocessor", Linear Algebra Appl. 77, 165-187.
7. George, A. and Liu, J.W.H. (1981) Computer Solution of Large Sparse Positive Definite Systems (Prentice-Hall, Englewood Cliffs, NJ).
8. Heath, M.T., Ng, E. and Peyton, B.W. (1991) "Parallel algorithms for sparse linear systems", SIAM Rev. 33.3, 420-460.
9. Levin, P.L. and Ludwig, R. (2002) "Crossroads for mixed-signal chips", IEEE Spectrum 39.3, 38-43.
10. Liu, J.W.H. (1990) "The role of elimination trees in sparse factorization", SIAM J. Matrix Anal. Appl. 11.1, 134-172.
11. Liu, J.W.H. (1992) "The multifrontal method for sparse matrix solution: theory and practice", SIAM Rev. 34.1, 82-109.
12. Liu, J.W.H. (1989) "The multifrontal method and paging in sparse Cholesky factorization", ACM Trans. Math. Software 15.4, 310-325.
13. Matrix Market, BCSSTK01 Test Matrix, http://math.nist.gov/MatrixMarket/ data/Harwell-Boeing/bcsstruc1/bcsstk01.html, (referred to in: 2003).
14. Shaw, K.A. and Dally, W.J. (2002) "Migration in single chip multiprocessors", Comput. Arch. Lett. 1.3, 2-5.
15. Wang, X. and Ziavras, S.G. (2004) "Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines", Concurrency Comput. Pract. Experience 16.4, 319-343.
16. Wang, X. and Ziavras, S.G. (2003) "Parallel Direct Solution of Linear Eqautions on FPGA-Based Machines", 11th Int. Conf. Paral. Distr. Real-Time Syst., Nice, France, April 22-23.
17. Xu, X. and Ziavras, S.G. (2003) "Iterative Methods for Solving Linear Systems of Equations on FPGA-Based Machines", 18th Int. Conf. Comput. Appl., Honolulu, Hawaii, March 26-28.