Static analysis for Fast and accurate design space exploration of caches

Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

Volumn , Issue , 2008, Pages 103-108

  Liang, Yun ^a   Mitra, Tulika ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Cache; Design space exploration; Probabilistic cache states

Indexed keywords

ACCURATE DESIGNS; ANALYSIS TECHNIQUES; APPLICATION-SPECIFIC SYSTEMS; AVERAGE ERRORS; BASIC BLOCKS; CACHE; CACHE CONFIGURATIONS; CACHE HIT RATES; CONTROL FLOWS; DESIGN POINTS; DESIGN SPACE EXPLORATION; EMBEDDED BENCHMARKS; HIT RATES; INSTRUCTION CACHES; ONE PASS; OPTIMAL PERFORMANCE; PROBABILISTIC CACHE STATES; PROGRAM CONTROLS; PROGRAM EXECUTIONS; STRUCTURAL SIMILARITIES; TRACE-DRIVEN SIMULATIONS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BENCHMARKING; CODES (SYMBOLS); CONCURRENCY CONTROL; DESIGN; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; SPACE RESEARCH; STATIC ANALYSIS;

EMBEDDED SYSTEMS;

EID: 63349099764     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1450135.1450159     Document Type: Conference Paper

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