Model checking SystemC designs using timed automata

Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

Volumn , Issue , 2008, Pages 131-136

  Herber, Paula ^a   Fellmuth, Joachim ^a   Glesner, Sabine ^a  

^a TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

Author keywords

Model checking; SystemC; Timed automata

Indexed keywords

AUTOMATA THEORY; EMBEDDED SYSTEMS; FORMAL METHODS; INFORMATION THEORY; INTEGRATED CIRCUITS; LOGIC DESIGN; ROBOTS; SEMANTICS; TIME MEASUREMENT; TIMING CIRCUITS; TRANSLATION (LANGUAGES);

DEADLOCK FREEDOMS; FORMAL SEMANTICS; HARDWARE/SOFTWARE CO DESIGNS; LIVENESS; MODEL CHECKERS; MODELING AND SIMULATIONS; SYSTEMC; SYSTEMC DESIGNS; TIMED AUTOMATA; TIMING CONSTRAINTS; TIMING PROPERTIES; TOOL SUITES; UPPAAL MODEL CHECKERS; VISUALIZATION TOOLS;

MODEL CHECKING;

EID: 63349089817     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1450135.1450166     Document Type: Conference Paper

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