Region of nearly constant off current versus gate length characteristics for sub-0.1 μm low power CMOS technology

2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC

Volumn , Issue , 2008, Pages

  Lau, W S ^a   Yang, Peizhen ^a   Ng, Edwin T L ^a   Chian, Z W ^a   Ho, V ^b   Siah, S Y ^b   Chan, L ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; SOLID STATE DEVICES; THRESHOLD VOLTAGE; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

GATE LENGTHS; INFLECTION POINTS; LOW POWER CMOS; MOS TRANSISTORS; OFF CURRENTS;

CURRENT VOLTAGE CHARACTERISTICS;

EID: 63249090042     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2008.4760689     Document Type: Conference Paper

References (7)

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