Leff extraction for sub-100 nm MOSFET devices

Solid-State Electronics

Volumn 48, Issue 1, 2004, Pages 163-166

  Ye, Qiuyi ^a,b   Biesemans, Serge ^b  

^a INFINEON TECHNOLOGIES   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

Integrated circuit; MOSFET's; Semiconductor devices; Transistors

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; SEMICONDUCTOR DEVICES;

DRAIN-INDUCED-BARRIER-LOWERING (DIBL) EFFECT;

MOSFET DEVICES;

EID: 0142185181     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(03)00076-5     Document Type: Article

References (7)

1. Taur Y., Zicherman D.S., Lombardi D.R., Restle Phillip J., Hsu C.H., Hanafi Hussein I., Wordeman Matthew R., Davari Bijan, Shahidi Ghavam G. A new 'shift and ratio' method for MOSFET channel-length extraction. IEEE Electron Dev. Lett. EDL-13:1992;267-269.
2. Biesemans S., Hendricks M., Kubicek, De Meyer K. Accurate determination of channel length, series resistance and junction doping profile for MOSFET optimization in deep sub. +- micron technologies VLSI Symp. 1996;166-167.
3. Guo J.C., Chung S.S., Hsu C.C. A new approach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET's. IEEE Trans. Electron Dev. ED-41:1994;1811-1818.
4. Ye Qiuyi, Li Yujun, Tonti W, Berry W, Parks C, Mohler R. Improving the accuracy of "shift and ratio": channel length extraction method in deep submicron technology. IEEE IRW Final Report 2000, 2000. p. 102-3.
5. Yang K., Hu C. MOS capacitance measurements for high-leakage thin dielectrics. IEEE Trans. Electron Dev. ED-46:1999;1500-1501.
6. Liu Zhi-Hong, Hu Chenming, Huang Jian-Hui, Chan Tung-Yi, Jeng Min-Chie, K Ping, Ko Threshold voltage model for deep-sub-micrometer MOSFET's. IEEE Trans. Electron Dev. ED-40:1993;86-95.
7. Brews J.R., Fichtner W., Nicollian E.H., Sze S.M. Generalized guide for MOSFET miniaturization. IEEE Electron Dev. Lett. EDL-1:1980;2-4.