Microprocessor-based system test using debug interface

Norchip - 26th Norchip Conference, Formal Proceedings

Volumn , Issue , 2008, Pages 98-101

  Devadze, Sergei ^a   Jutman, Artur ^a   Tsertov, Anton ^b   Instenberg, Martin ^c   Ubar, Raimund ^b  

^a Testonica Lab   (Estonia)

^b TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

^c ILMENAU UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRANSFER; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; POLYCHLORINATED BIPHENYLS; PRINTED CIRCUIT MANUFACTURE; SEMICONDUCTOR DEVICE MANUFACTURE;

BOUNDARY SCAN TECHNIQUES; DESIGN CONSTRAINTS; ELECTRONIC MANUFACTURING; HARDWARE DESIGNS; HARDWARE OVERHEADS; PCB ASSEMBLIES; SEMICONDUCTOR TECHNOLOGIES; SYSTEM TESTS; SYSTEM-LEVEL TESTS; TEST COVERAGES;

TESTING;

EID: 63049139060     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NORCHP.2008.4738291     Document Type: Conference Paper

References (20)

1. A.H. Robbins, B. Lundeen. Troubleshooting Microprocessor-Based Systems. Prentice-Hall, 1987, 320 p.
2. H.K. Reghbati. Tutorial: VLSI Testing & Validation Techniques. IEEE Computer Society Press, 1985, 603 p.
3. K.P. Parker. The Boundary-Scan Handbook. Kluwer Academic Publishers, Boston, MA, USA, 2003, 373 p.
4. IEEE Std. 1149.1-2001, IEEE Standard test access port and boundaryscan architecture, 2001.
5. B. Al-Hashimi. System-on-chip: Next Generation Electronics. The Institution of Engineering and Technology Press, 2006, 911 p.
6. IEEE Std. 1500, Standard Testability Method for Embedded Corebased Integrated Circuits, 2007.
7. D. Gizopoulos, A. Paschalis, Y. Zorian. Embedded Processor-Based Self-Test. Kluwer Academic Publishers, Boston, USA, 2004, 217 p.
8. th IEEE Int. On-Line Testing Symp. (IOLTS 07), Hersonissos-Heraklion, Greece, July 8-11, 2007, pp. 277-284.
9. S.K. Lim, "Physical design for 3D system on package", IEEE Design & Test of Computers, vol.22, no.6, 2005, pp. 532-539.
10. B. Nadeau-Dostie, et.al, "An Embedded Technique for At-Speed Interconnect Testing," in Proc. Int. Test Conf. (ITC'99), Atlantic City, NJ, USA, Sept 28-30, 1999, pp. 431-438.
11. th IEEE European Test Symposium (ETS'04), France, 2004, pp. 2-7.
12. H. Ehrenberg, Bob Russell, B. Van Treuren, "IEEE P1581 - Getting More Board Test Out of Boundary Scan", in Proc. Int. Test Conference (ITC'06), Santa Clara, USA, Oct 22-27, 2006, pp. 1-10.
13. B. Eklow, C. Barnhart, M. Ricchetti, T. Borroz, "IEEE 1149.6 - a practical perspective", In Proc. Int. Test Conference (ITC'03), Charlotte, NC, USA, Sep 30-Oct 2, 2003, pp. 70-78.
14. IEEE Std. 1149.6, IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks, 2003.
15. D.A Bonnett, "Design for In-System Programming", in Proc. Int. Test Conference (ITC'99), Atlantic City, NJ, USA, Sept 28-30, 1999, pp. 252-259.
16. The Nexus 5001 Forum "Standard for a Global Embedded Processor Debug Interface Version 2.0
17. MIPI Alliance Recommendation for Test & Debug: Debug and Trace Connectors
18. IEEE P1149.7, Standard for Reduced-pin and Enhanced-functionality Test Access Port and Boundary Scan Architecture, proposal.
19. MIPI Alliance Inc. T&D WG White paper on MIPI NIDnT-Port.
20. D. Lampret. OpenRISC 1200 IP Core Specification. opencores.org, 2001. Revision 0.7.