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Volumn , Issue , 2008, Pages 897-902

Joint reliability of double-side packaged SiC power devices to a DBC substrate with high temperature solders

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM NITRIDE; ALUMINUM OXIDE; BINARY ALLOYS; CHIP SCALE PACKAGES; DIES; ELECTRIC RESISTANCE; ELECTRODES; III-V SEMICONDUCTORS; LEAD ALLOYS; METALLIZING; OXIDE FILMS; RELIABILITY; SILICON CARBIDE; SILVER; STUDS (FASTENERS); STUDS (STRUCTURAL MEMBERS); SUBSTRATES;

EID: 63049118291     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2008.4763544     Document Type: Conference Paper
Times cited : (8)

References (14)
  • 2
    • 63049110453 scopus 로고    scopus 로고
    • Introduction to Power Electronics Packaging, Evolution of powering architectures, [Online]. Available: http://www.nmrc.ie/resear ch/maigroup/power-intro.html.
    • Introduction to Power Electronics Packaging, "Evolution of powering architectures", [Online]. Available: http://www.nmrc.ie/resear ch/maigroup/power-intro.html.
  • 3
    • 0035333517 scopus 로고    scopus 로고
    • High-power robust semiconductor electronics technologies in the new millennium
    • K. Shenai, "High-power robust semiconductor electronics technologies in the new millennium," Microelectron. Journal, Vol. 32, No. 5-6, pp. 397-408, 2001.
    • (2001) Microelectron. Journal , vol.32 , Issue.5-6 , pp. 397-408
    • Shenai, K.1
  • 4
    • 63049104413 scopus 로고    scopus 로고
    • Silicon carbide power applications and device roadmap
    • J. Richmond, S. Hodge, and J. Palmour, "Silicon carbide power applications and device roadmap," Power Electron Europe, Issue 7, pp. 17-21, 2004.
    • (2004) Power Electron Europe , Issue.7 , pp. 17-21
    • Richmond, J.1    Hodge, S.2    Palmour, J.3
  • 5
    • 63049102874 scopus 로고    scopus 로고
    • A. Agarwal, R. Singh, S.H. Ryu, J. Richmond, C. Capell, S. Schwab, B. Moore and J. Pamour. CPWR-TECH1, Cree, Inc. [Online]. Available: http://www.cree.com/products/power.asp
    • A. Agarwal, R. Singh, S.H. Ryu, J. Richmond, C. Capell, S. Schwab, B. Moore and J. Pamour. CPWR-TECH1, Cree, Inc. [Online]. Available: http://www.cree.com/products/power.asp
  • 6
    • 63049100327 scopus 로고    scopus 로고
    • C. Bull, Trends in power semiconductor packaging, ECNMag., Sep. 2000.
    • C. Bull, "Trends in power semiconductor packaging", ECNMag., Sep. 2000.
  • 7
    • 24644494367 scopus 로고    scopus 로고
    • Three-dimensional packaging for power semiconductor devices and modules
    • Aug
    • J. N. Calata, J.B. Bai, X. Liu, S. Wen, and G.-Q. Lu, "Three-dimensional packaging for power semiconductor devices and modules," IEEE Trans. Adv. Packag., vol. 28, no. 3, pp. 404-412. Aug. 2005.
    • (2005) IEEE Trans. Adv. Packag , vol.28 , Issue.3 , pp. 404-412
    • Calata, J.N.1    Bai, J.B.2    Liu, X.3    Wen, S.4    Lu, G.-Q.5
  • 9
    • 0342499775 scopus 로고
    • Flip chip assemblies using conventional wire bonding apparatus and commercially available dies
    • Dallas, pp
    • H. Montgomery, "Flip chip assemblies using conventional wire bonding apparatus and commercially available dies," in Proc. ISHM, Dallas, pp. 451-456, 1993.
    • (1993) Proc. ISHM , pp. 451-456
    • Montgomery, H.1
  • 11
    • 0008163049 scopus 로고    scopus 로고
    • Flip Chip Mounting Using Stud Bumps and Adhesive for Encapsulation
    • Lau J. H, ed, McGraw-Hill, New York, pp
    • K. Tsunoi, T. Kusagaya, and H. Kira, "Flip Chip Mounting Using Stud Bumps and Adhesive for Encapsulation," in Flip Chip Technology, Lau J. H., ed., McGraw-Hill, New York, pp. 357-366, 1996.
    • (1996) Flip Chip Technology , pp. 357-366
    • Tsunoi, K.1    Kusagaya, T.2    Kira, H.3
  • 13
    • 0037351928 scopus 로고    scopus 로고
    • Gold stud bumps in flip chip applications
    • Jordan, "Gold stud bumps in flip chip applications", Microw. Journal, pp. 86-103, 2003.
    • (2003) Microw. Journal , pp. 86-103
    • Jordan1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.