Three-dimensional packaging for power semiconductor devices and modules

IEEE Transactions on Advanced Packaging

Volumn 28, Issue 3, 2005, Pages 404-412

  Calata, Jesus N ^a   Bai, John G ^a   Liu, Xingsheng ^b   Wen, Sihua ^c   Lu, Guo Quan ^a  

^a State University   (United States)

^b Corning Inc ^*  (United States)

^c Allegro MicroSystems Inc   (United States)

Author keywords

Dimple array interconnect; Direct solder interconnect; Metal posts interconnected parallel plate structure; Packaging; Power electronics; Power semiconductor devices; Stacked solder bumping; Three dimensional (3 D) packaging

Indexed keywords

MULTICHIP MODULES; POWER CONVERTERS; POWER ELECTRONICS; SEMICONDUCTOR DEVICES;

DIRECT SOLDER INTERCONNECT; POWER SEMICONDUCTOR DEVICES; STACKED SOLDER BUMPING; THREE DIMENSIONAL PACKAGING;

ELECTRONICS PACKAGING;

EID: 24644494367     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2005.852837     Document Type: Article

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