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Volumn , Issue , 2008, Pages 533-538

Analysis of thermal performance of high power light emitting diodes package

Author keywords

Conversion efficiency; Finite element analysis; Forward voltage method; High power LED package

Indexed keywords

CONVECTION COEFFICIENTS; COPPER SLUGS; DESIGN FACTORS; DESIGN PARAMETERS; DIE-ATTACH MATERIALS; DOMINANT FACTORS; ELECTRO-OPTICAL; EXPERIMENTAL DATUM; FACTORIAL DESIGNS; FEM MODELS; FINITE ELEMENT ANALYSIS; FINITE ELEMENT ANALYSIS PROGRAMS; FINITE ELEMENT MODELS; FORWARD VOLTAGE METHOD; HIGH POWER LED PACKAGE; HIGH-POWER LIGHT-EMITTING DIODES; INPUT POWER; JUNCTION TEMPERATURES; LIFE SPANS; MANUFACTURING PROCESS; SIMULATION ANALYSIS; SIMULATION RESULTS; THERMAL CHARACTERISTICS; THERMAL MANAGEMENTS; THERMAL PERFORMANCE;

EID: 63049112163     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2008.4763488     Document Type: Conference Paper
Times cited : (31)

References (9)
  • 5
    • 0035389454 scopus 로고    scopus 로고
    • Thermal/Mechanical Analysis of Novel C-TSOP Using Nonlinear FEM Method
    • J. C. Lin and K. N. Chiang, "Thermal/Mechanical Analysis of Novel C-TSOP Using Nonlinear FEM Method," Journal of the Chinese Institute of Engineers, Vol. 24, No. 4, pp. 453-462, 2001
    • (2001) Journal of the Chinese Institute of Engineers , vol.24 , Issue.4 , pp. 453-462
    • Lin, J.C.1    Chiang, K.N.2
  • 6
    • 63049096729 scopus 로고    scopus 로고
    • Thermal management on hot spot elimination / junction temperature reduction for high power density system in package structure
    • C. Y. Chou, C. J. Wu, H. P. Wei, M. C. Yew, C. C. Chiu and K. N. Chiang, "Thermal management on hot spot elimination / junction temperature reduction for high power density system in package structure," International E
    • International E
    • Chou, C.Y.1    Wu, C.J.2    Wei, H.P.3    Yew, M.C.4    Chiu, C.C.5    Chiang, K.N.6
  • 7
    • 63049108723 scopus 로고    scopus 로고
    • JEDEC Standard EIA/JESD51-1, Integrated Circuits Thermal Measurement Method-Electrical Test Method (Single Semiconductor Device), 1995
    • JEDEC Standard EIA/JESD51-1, "Integrated Circuits Thermal Measurement Method-Electrical Test Method (Single Semiconductor Device)," 1995


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.