SCOPUS 정보 검색 플랫폼

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2008, Pages 709-712

An FPGA implementation of a DWT with 5/3 filter using semi-programmable hardware

(3) Yamawaki, Akira a Morita, Kazuharu a Iwane, Masahiko a

a KYUSHU INSTITUTE OF TECHNOLOGY (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA-PREFETCHING; EFFICIENT DESIGNS; FPGA IMPLEMENTATIONS; HARDWARE IMPLEMENTATIONS; IMPROVE-A; JPEG-2000; MAPPING METHODS; MEMORY ACCESS LATENCIES; MEMORY ACCESS PATTERNS; PROGRAMMABLE HARDWARES;

DISCRETE WAVELET TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); WAVELET DECOMPOSITION;

HARDWARE;

EID: 62949216878 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/APCCAS.2008.4746122 Document Type: Conference Paper

Times cited : (2)

References (7)

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- Angelopoulou, M.E.¹ Masselos, K.² Cheung, P.Y.K.³ Andreopoulos, Y.⁴

2
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- Using global code motions to improve the quality of results for high-level synthesis
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- Gupta, S.¹ Savoiu, N.² Dutt, N.³ Gupta, R.⁴ Nicolau, A.⁵

3
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- Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines
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- Park, J.¹ Diniz, P.C.²

4
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- Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions
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- Lau, D.¹ Pritchard, O.² Molson, P.³

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- Agility, DK design suite, http://www.agilityds.com/products/ c-based-products/dk-de-sign-suite/, 2008.
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6
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- in C. Prentice Hall
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7
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- Data Prefetch Mechanisms
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.