An efficient CPLD technology mapping under the time constraint

Proceedings of the International Conference on Microelectronics, ICM

Volumn 2000-October, Issue , 2000, Pages 265-268

  Kim, Hi Seok ^a   Kim, Jae Jin ^a   Lin, Chi Ho ^b  

^a Chongju University   (South Korea)

^b Semyung University   (South Korea)

Author keywords

feasible cluster; number of multi level; technology mapping for CPLD; time constraint

Indexed keywords

ALGORITHMS; BOOLEAN ALGEBRA; CONFORMAL MAPPING; LOGIC DEVICES; MAPPING; MICROELECTRONICS;

BOOLEAN EQUATIONS; BOOLEAN NETWORKS; FEASIBLE CLUSTER; LOGIC BLOCKS; MULTILEVELS; TECHNOLOGY MAPPING; TECHNOLOGY MAPPING ALGORITHMS; TIME CONSTRAINTS;

CLUSTERING ALGORITHMS;

EID: 84979498124     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.2000.916457     Document Type: Conference Paper

References (9)

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