Neural cache: A low-power online digital spike-sorting architecture

Proceedings of the 30th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS'08 - "Personalized Healthcare through Technology"

Volumn , Issue , 2008, Pages 2004-2007

  Peng, Chung Ching ^a   Sabharwal, Pawan ^a   Bashirullah, Rizwan ^a  

^a J Crayton Pruitt Family Department of Biomedical Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA BANDWIDTHS; ENERGY SAVINGS; LARGE AMOUNTS OF DATUM; LEAKAGE POWER; LOW FREQUENCIES; LOW-POWER; LOW-POWER ARCHITECTURES; MULTI-ELECTRODE ARRAYS; NEURAL DATUM; NEURAL RECORDINGS; NEURAL SPIKES; NON STATIONARIES; POWER CONSUMPTION; SCALED CMOS; SPIKE SORTING ALGORITHMS; SPIKE-SORTING; WIRELESS DATA TRANSMISSIONS;

SORTING;

ACTION POTENTIAL; ALGORITHM; ARTICLE; BIOLOGICAL MODEL; BRAIN; CLUSTER ANALYSIS; EQUIPMENT; HUMAN; PHYSIOLOGY; POWER SUPPLY; PROSTHESES AND ORTHOSES; SIGNAL PROCESSING;

ACTION POTENTIALS; ALGORITHMS; BRAIN; CLUSTER ANALYSIS; ELECTRIC POWER SUPPLIES; HUMANS; MODELS, NEUROLOGICAL; PROSTHESES AND IMPLANTS; SIGNAL PROCESSING, COMPUTER-ASSISTED;

EID: 61849168189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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