Power feasibility of implantable digital spike-sorting circuits for neural prosthetic systems

Annual International Conference of the IEEE Engineering in Medicine and Biology - Proceedings

Volumn 26 VI, Issue , 2004, Pages 4237-4240

  Zumsteg, Zachary S ^a   Ahmed, Rizwan E ^a   Santhanam, Gopal ^a   Shenoy, Krishna V ^a,b   Meng, Teresa H ^a  

^a Stanford University   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

Neural prosthetics; Power estimation; Spike sorting algorithms; Spike sorting circuits

Indexed keywords

ALGORITHMS; BRAIN; HUMAN REHABILITATION EQUIPMENT; MICROELECTRODES; NEUROLOGY; PROSTHETICS;

NEURAL PROSTHETICS; POWER ESTIMATION; SPIKE SORTING ALGORITHMS; SPIKE SORTING CIRCUITS;

IMPLANTS (SURGICAL);

EID: 11144291417     PISSN: 05891019     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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