Parameterizable architecture-level SRAM power model using circuit-simulation backend for leakage calibration

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 557-563

  Do, Minh Q ^a   Drazdziulis, Mindaugas ^a   Larsson Edefors, Per ^a   Bengtsson, Lars ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT-LEVEL SIMULATION; DYNAMIC POWER ESTIMATION; HYBRID METHOD; LEAKAGE POWER; MEMORY COMPONENT; MEMORY SIZE; POWER ESTIMATION METHOD; STATIC LEAKAGE;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ESTIMATION; STATIC RANDOM ACCESS STORAGE;

SPICE;

EID: 34547316288     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.97     Document Type: Conference Paper

References (9)

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