An implementation of the SANE Virtual Processor using POSIX threads

Journal of Systems Architecture

Volumn 55, Issue 3, 2009, Pages 162-169

  van Tol, M W ^a   Jesshope, C R ^a   Lankamp, M ^a   Polstra, S ^a  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

Author keywords

Concurrent programming model; Microthreading; POSIX threads; SVP implementation

Indexed keywords

COMPUTER SOFTWARE;

C++ LIBRARIES; C++ SYNTAXES; CONCURRENT PROGRAMMING MODEL; CONVENTIONAL SYSTEMS; DEADLOCK FREE; EFFICIENT IMPLEMENTATIONS; FPGA CHIPS; MICROTHREADING; PORTABLE IMPLEMENTATIONS; POSIX THREADS; PROGRAMMING LANGUAGES; SVP IMPLEMENTATION; VIRTUAL PROCESSORS;

REAL TIME SYSTEMS;

EID: 61749097400     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2008.09.006     Document Type: Article

References (18)

1. C.R. Jesshope, SVP and μTC - a dynamic model of concurrency and its implementation as a compiler target, .
2. C.R. Jesshope, Microthreading a model for distributed instruction-level concurrency, Parallel Processing Letters 16(2) (2008) 209-228, ISSN:0129-6264.
3. K. Bousias, C.R. Jesshope, The challenges of massive on-chip concurrency, in: Tenth Asia-Pacific Computer Systems Architecture Conference, LNCS, vol. 3740, 2005, Springer-Verlag, Singapore, pp. 24-26.
4. C.R. Jesshope, μTC - an intermediate language for programming chip multiprocessors, in: Proceedings of the Pacific Computer Systems Architecture Conference 2006 - ACSAC06, ISBN 3-540-4005, vol. 4186, LNCS, pp. 147-160.
5. CERN, The CINT C/C++ Interpreter project homepage, .
6. AETHER project homepage, .
7. T.A.M. Bernard, C.R. Jesshope, P.M.W. Knijnenburg, Strategies for compiling μTC to novel chip multiprocessors, in: S. Vassiliadis et al. (Eds.), International Symposium on Systems, Architectures, MOdeling and Simulation, SAMOS 2007, vol. 4599, LNCS, 2007, pp. 127-138.
8. C99 ISO/IEC 9899 International standard, 1999, .
9. C. Grelck, S.B. Scholz, A. Shafarenko, S-Net: a typed stream processing language, in: Proceedings of the 18th International Symposium on Implementation and Application of Functional Languages (IFL'06), Budapest, Hungary, September 4-6, 2006, pp. 81-97.
10. Scholz S.B. Single assignment C - efficient support for high-level array operations in a functional setting. Journal of Functional Programming 13 6 (2003) 1005-1053
11. ACE: CoSy Compiler Development System, .
12. Hagersten E., Landin A., and Haridi S. DDM - a cache-only memory architecture. IEEE Computer 25 9 (1992) 44-54
13. L. Zhang, C.R. Jesshope, On-chip COMA cache-coherence protocol for microgrids of microthreaded cores, Presented at and submitted to Proceedings of the Workshop on Highly Parallel Processing on a Chip (HPPC), Associated with Euro-Par 2007.
14. M. Lankamp, Developing a reference implementation for a microgrid of microthreaded microprocessors, M.Sc. Thesis, Faculty of Science, Computer Systems Architecture group, University of Amsterdam, 2007.
15. J. Kadlec, R. Bartosinski, M. Danek, Accelerating microblaze floating point operations, in: Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), Delft, IEEE, 2007 - (K. Bertels, W. Najjar, A. Genderen, S. Vassiliadis, International Conference on Field Programmable Logic and Applications. FPL 2007. Amsterdam NL, pp. 621-624. ISBN:1-4244-1060-6, 27.08.2007-29.08.2007).
16. UTIA website, .
17. Xilinx, MicroBlaze Processor Reference Guide, 2007.
18. Xilinx, Xilkernel Manual, 2006.