Relaxing synchronization in a parallel SystemC kernel

Proceedings of the 2008 International Symposium on Parallel and Distributed Processing with Applications, ISPA 2008

Volumn , Issue , 2008, Pages 180-187

  Combes, Philippe ^a   Caron, Eddy ^a   Desprez, Frédéric ^a   Chopard, Bastien ^b   Zory, Julien ^c  

^a UNIVERSITÉ DE LYON   (France)

^b UNIVERSITY OF GENEVA   (Switzerland)

^c STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN MODELS; EXPLORATION POTENTIALS; SIMULATION TIME; SOC DESIGNS; SYSTEM-ON-CHIP DEVICES; SYSTEMC; TIME TO MARKETS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DISTRIBUTED PARAMETER NETWORKS; INDUSTRIAL APPLICATIONS; INFORMATION THEORY; INTEGRATED CIRCUITS; SYNCHRONIZATION;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 60749090018     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPA.2008.124     Document Type: Conference Paper

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