SAVANT/TyVIS/warped: components for the analysis and simulation of VHDL

Proceedings - IEEE International Verilog HDL Conference

Volumn , Issue , 1998, Pages 195-201

  Wilsey, Philip A ^a   Martin, Dale E ^a   Subramani, Krishnan ^a  

^a Computer Architecture Design Lab ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER ARCHITECTURE; COMPUTER NETWORKS; COMPUTER SIMULATION; DATA STRUCTURES; INTERFACES (COMPUTER); PARALLEL ALGORITHMS;

INDUSTRIAL RESEARCH PROGRAMS; SAVANT PROJECT; VERILOG HARDWARE DESCRIPTION LANGUAGE;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0031654310     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)