A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 547-550

  Wu, Ting ^a,b   Hanumolu, Pavan Kumar ^a   Mayaram, Kartikeya ^a   Moon, Un Ku ^a  

^a Oregon State University   (United States)

^b RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY SYNTHESIZERS; INTEGRATED CIRCUITS; PHASE NOISE; VARACTORS;

CMOS PROCESSS; FREQUENCY TUNING RANGE; INTEGER-N; LOCK TIME; PLL FREQUENCY SYNTHESIZER; PROTOTYPE TESTS; SETTLING TIME; SWITCHED CAPACITOR INTEGRATOR;

VARIABLE FREQUENCY OSCILLATORS;

EID: 59349121565     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405791     Document Type: Conference Paper

References (8)

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