An improved wideband PLL with adaptive frequency response that tracks the reference

Proceedings of the Custom Integrated Circuits Conference

Volumn 2005, Issue , 2005, Pages 549-552

  Hufford, Michael ^a   Naviasky, Eric ^a   Williams, Steve ^a   Williams, Michelle ^a  

^a Cadence Design Services   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BROADBAND NETWORKS; CAPACITORS; ELECTRIC FREQUENCY CONTROL; FEEDBACK; FREQUENCY RESPONSE; SYNCHRONIZATION; VARIABLE FREQUENCY OSCILLATORS;

FEEDBACK RATIO; FREQUENCY RESPONSE TRACKING; OPEN LOOP FREQUENCY; PROCESS VARIATIONS;

PHASE LOCKED LOOPS;

EID: 33847132802     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568727     Document Type: Conference Paper

References (6)

1. L. Sun, D. Nelson, "A 1.0V GHz Range 0.13μm CMOS Frequency Synthesizer," IEEE Custom Integrated Circuits Conference, 2001, p. 327.
2. J. Maneatis, J. Kim, I. McClatchie. J. Maxey, and M. Shankaradas, "Self-Biased High-Bandwidth Low Jitter 1-4096 Multiplier Clock Generator PLL" IEEE Journal of Solids-State Circuits, vol 38, pp 1795-1803, Nov. 2003.
3. A. Maxim, "A 2-5GHz Low Jitter 0.13um CMOS PLL Using a Dynamic Current Matching Charge-pump and a Noise Attenuation Loop-Filter", IEEE Custom Integrated Circuits Conference, 2004, p. 147.
4. A. Maxim, B. Scott, E. Schneider, M. Hagge, S. Chacko, and D. Stiurca, "A Low-Jitter 125-1250-MHz Process-Independent and Ripple-Poleless 0.18-um CMOS PLL Based on a Sample-Reset Loop Filter" IEEE Journal of Solid-State Circuits, vol 36, pp. 1673-1683, Nov. 2001
5. S. Williams, H. Thompson, M. Hufford and E. Naviasky, "An Improved CMOS Ring Oscillator PLL with Less than 4ps RMS Accumulated Jitter," IEEE Custom Integrated Circuits Conference, 2004, pp. 151-154.
6. J. Craninckx, M. S. J. Steyaert, "A Fully Integrated CMOS DCS-1800 Frequency Synthesizer," IEEE Journal of Solid State Circuits, vol. 33, pp. 2056-2057, Dec. 1998.