Correlation of PDN impedance with jitter and voltage margin for high speedchannels

Electrical Performance of Electronic Packaging, EPEP

Volumn , Issue , 2008, Pages 73-76

  Laddha, Vishal ^a   Swaminathan, Madhavan ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED PARAMETER NETWORKS; DISTRIBUTION OF GOODS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER DISTRIBUTION; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; SANITARY SEWERS;

CUT-OUTS; DESIGN PRACTICES; DIGITAL CHANNELS; HIGH SPEEDS; INDUCED SIGNALS; POWER DISTRIBUTION NETWORKS; SIGNAL INTERCONNECTS; SIMULATIONS AND MEASUREMENTS; SIMULTANEOUS SWITCHING NOISES; TIMING MARGINS; VOLTAGE MARGINS;

JITTER;

EID: 58049124944     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2008.4675880     Document Type: Conference Paper

References (8)

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