Reduction of VCO phase noise through forward substrate biasing of switched MOSFETs

ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Volumn , Issue , 2008, Pages 326-329

  Šiprak, Domagoj ^a   Tiebout, Marc ^b   Baumgartner, Peter ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

MOSFET DEVICES; PHASE NOISE; SUBSTRATES;

1/F NOISES; CARRIER PHASE; GATE BIASES; LARGE SIGNALS; MOS FETS; PHYSICAL EFFECTS; SUBSTRATE BIASES; SUBSTRATE BIASING;

VARIABLE FREQUENCY OSCILLATORS;

EID: 58049100430     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2008.4681858     Document Type: Conference Paper

References (5)

1. A.P. van der Wel et al., "Low-Frequency Noise Phenomena in Switched MOSFETs," IEEE J. Solid-State Circuits, vol. 42 (3), pp. 540-550, March 2007.
2. D. Šiprak, N. Zanolla, M. Tiebout, P. Baumgartner, and C. Fiegna, "Reduction of Low-Frequency Noise in MOSFETs under Switched Gate and Substrate Bias," Proc. ESSDERC/ESSCIRC 2008, in press.
3. T. Schiml et al., "A 0.13μm CMOS Platform with Cu/Low-k Inter-conects for System On Chip Applications," VLSI 2001, pp. 101 -102.
4. J.S. Kolhatkar, Ph.D. thesis, University of Twente, 2005.
5. D. Miyashita et al., "A Phase Noise Minimization of CMOS VCOs over Wide Tuning Range and Large PVT Variations," Proc. C1CC 2005, pp. 583-586, 2005.