A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS

ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Volumn , Issue , 2008, Pages 410-413

  Borremans, J ^a,b   Ryckaert, J ^a   Wambacq, P ^a,b   Kuijk, M ^b   Craninckx, J ^a  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

PHASE NOISE;

BAND PHASE NOISES; LOW PHASE NOISES; LOW VOLTAGES; RING OSCILLATORS;

NETWORKS (CIRCUITS);

EID: 58049095527     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2008.4681879     Document Type: Conference Paper

References (6)

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6. S. Giekink, "An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL", Dig. of Tech. Papers, ISSCC 2008, pp. 454-455, Feb. 2008.