Model checking bluespec specified hardware designs

Proceedings - International Workshop on Microprocessor Test and Verification

Volumn , Issue , 2007, Pages 39-43

  Singh, Gaurav ^a   Shukla, Sandeep K ^a  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; HIGH LEVEL LANGUAGES; SPECIFICATION LANGUAGES;

ABSTRACTION TECHNIQUES; BEHAVIORAL PROPERTIES; COMPLEX HARDWARE; HARDWARE MODELS; HIGH LEVEL SPECIFICATION; LEVEL OF ABSTRACTION; MODEL CHECKING TOOLS; RTL (REGISTER TRANSFER LEVEL);

MODEL CHECKING;

EID: 57849150449     PISSN: 15504093     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTV.2007.9     Document Type: Conference Paper

References (6)

1. Arvind, R. Nikhil, D. Rosenband, and N. Dave, "High-level syn thesis: An Essential Ingredient for Designing Complex ASICs," Proceedings of the International Conference on Computer Aided Design (ICCAD'04), pp. 775-782, November 2004.
2. D. Rosenband and Arvind. "Modular Scheduling of Guarded Atomic Actions," Proceedings of the Design Automation Conference (DAC}()4), June 2004.
3. G. Holzmann. The SPIN Model Checker. Addison Wesley, 2004.
4. E. M. Clarke, O. Grumberg, and D. A. Peled, Model Cheeking. The MIT Press. 2000.
5. F. Theon and F. Catthoor, Modeling, Verification and, Exploration of Task-Level Concurrency in Real-Time Embedded Systems. Kluwcr Academic Publisher, 2000.
6. J. C. Hoe and Arvind, "Hardware Synthesis from Term Rewriting Systems." Proceeding of VLST99 Lisbon, Portugal, December 1999.