Yield model characterization for analog integrated circuit using pareto-optimal surface

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Volumn , Issue , 2008, Pages 1163-1166

  Ali, Sawal ^a   Wilcock, Reuben ^a   Wilson, Peter ^a   Brown, Andrew ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; LINEAR INTEGRATED CIRCUITS; MONTE CARLO METHODS; MULTIOBJECTIVE OPTIMIZATION; NETWORKS (CIRCUITS);

ANALOG INTEGRATED CIRCUITS; CIRCUIT DESIGNS; COMPUTATIONAL COSTS; DESIGN POINTS; MONTE CARLO SIMULATIONS; MULTI-OBJECTIVE OPTIMIZATIONS; NOVEL TECHNIQUES; OPTIMAL PERFORMANCES; OPTIMIZED DESIGNS; PARETO FRONTS; PERFORMANCE FUNCTIONS; TRANSISTOR LEVELS; YIELD MODELS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 57849122189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2008.4675065     Document Type: Conference Paper

References (12)

1. B.De Smedt and G.Gielen, "Watson: design space boundary exploration and model generation for analog and rfic design," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transaction on, vol.22, no.2, pp. 213-224, Feb. 2003.
2. F.Medeiro et al., "A statistical optimization based approach for automated sizing of analog cells, in Proc. Of 1994 IEEE/ACM International Conference on Computer Aided Design, pp. 594-597.
3. E.S. Ochotta, R.Rutenbar, and L.R. Carley, "Synthesis of high-performance analog circuits in ASTRX/OBLX," IEEE Trans. Computer -Aided Design, vol. 15, pp.273-294, Mar. 1996
4. R.Phelps, M. Krasnicki, R.A Rutenbar, L. Richard Carley and J.R.Hellums, "Anaconda:Simulation-based synthesis of Analog Circuits via stochastic pattern search," IEEE Trans. Computer-aided design of integrated circuits and systems, vol. 19, No.6, June 2000
5. M. Krasnicki, R.Phelps, R.A Rutenbar and L. Richard Carley, "MAELSTROM: efficient simulation-based synthesis for custom analog cells," in Proc. DAC 1999, pp 945-950.
6. M. Krasnicki, R.Phelps, R.A Rutenbar, L. Richard Carley, J.R.Hellums and M. McClung, "ASF: a practical simulation-based methodology for the synthesis of custom analog circuits," in Proc. ICCAD 2001, pp 350-357.
7. B. D. Smedt, G. Gielen, "HOLMES: Capturing the yield-optimized design space boundaries of analog and RF Integrated Circuits." In Proc. Of the Design, Automation and Test in Europe Conference and Exhibition, 2003
8. K. Deb, Multi-Objective Optimization Using Evolutionary Algorithms, John Wiley & Sons Ltd, 2001.
9. Hajela, P., Lee, E. and C.Y. , "Genetic Algorithms in structural topology optimization. In Proc. Of the NATO Advanced Research Workshop on Topology Design of Structures 1993, pp. 117-133.
10. D.E. Goldberg: "Genetic Algorithms in search, optimization and machine learning,"Addison-Wesley (1989).
11. R. Spence and R.S. Soin, "Tolerance Design of Electronic Circuits," Addison Wesley 1988.
12. D.Mueller, G.Stehr, H. Graeb and U. Schlichtmann, "Deterministic Approaches to Analog Performance Space Exploration (PSE)", in Proc. DAC 2005, pp 869-874.