A 10.3 Gb/s burst-mode CDR Using a ΔΣ DAC

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 12, 2008, Pages 2921-2928

  Terada, Jun ^a   Nishimura, Kazuyoshi ^a   Kimura, Shunji ^b   Katsurai, Hiroaki ^a   Yoshimoto, Naoto ^b   Ohtomo, Yusuke ^a  

^a NTT CORPORATION   (Japan)

^b NTT Access Network Service Systems Laboratories   (Japan)

Author keywords

High speed integrated circuits; Optical communication; Receivers; Sigma delta modulation

Indexed keywords

BICMOS TECHNOLOGY; DELTA MODULATION; DIGITAL INTEGRATED CIRCUITS; HYBRID COMPUTERS; INTEGRATED CIRCUITS; JITTER; MODULATION; MODULATORS; NETWORKS (CIRCUITS); OPTICAL COMMUNICATION; OSCILLATORS (ELECTRONIC); PHOTONICS; SEMICONDUCTING SILICON;

ANALOG CONVERTERS; CHARGE PUMPS; CLOCK AND DATA RECOVERY CIRCUITS; DIGITAL FREQUENCIES; EXTERNAL-; FREQUENCY ERRORS; HIGH-SPEED INTEGRATED CIRCUITS; JITTER TOLERANCES; MEASUREMENT RESULTS; RECEIVERS; SIGE BICMOS; SIGMA-DELTA MODULATION; SIMULATION RESULTS; VOLTAGE-CONTROLLED OSCILLATORS;

DELTA SIGMA MODULATION;

EID: 57849107741     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2006229     Document Type: Conference Paper

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