A burst-mode bit-synchronization IC with large tolerance for pulse-width distortion for gigabit ethernet PON

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 11, 2006, Pages 2555-2565

  Tagami, Hitoyuki ^b   Kozaki, Seiji ^b   Nakura, Kenich ^b   Kohama, Shigeki ^b   Nogami, Masamichi ^b   Motoshima, Kuniaki ^a,b  

^a IEEE   (Japan)

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

BiCMOS integrated circuits; Integrated circuits (ICs); Optical communication; Optical receivers; Phase synchronization; Phase locked loops (PLLs); Synchronization

Indexed keywords

BICMOS INTEGRATED CIRCUITS; OPTICAL RECEIVERS; PASSIVE OPTICAL NETWORK (PON); PHASE SYNCHRONIZATION;

BIT ERROR RATE; DETECTORS; ELECTRIC DISTORTION; ELECTRIC LINES; ELECTRIC TRANSFORMERS; OPTICAL COMMUNICATION; PULSE WIDTH MODULATION; SYNCHRONIZATION;

INTEGRATED CIRCUITS;

EID: 33750843393     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.883318     Document Type: Conference Paper

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