Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2008, Pages 17-18

  Cai, M ^a   Greene, B J ^a   Strane, J ^a   Belyansky, M ^a   Tamweber, F ^a   Lee, D ^a   Van Meer, H ^a   Laffosse, E ^a   Luning, S ^a   Mocuta, D ^a   Maciejewski, E ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; NANOTECHNOLOGY;

32 NM TECHNOLOGIES; 32NM NODES; DUAL STRESS LINERS; GATE LENGTHS; SOI CMOS;

HIGH PERFORMANCE LIQUID CHROMATOGRAPHY;

EID: 57749202052     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2008.4656273     Document Type: Conference Paper

References (3)

1. S. Ito et al., "Mechanical Stress Effect of etch-stop nitride and its impact on deep submicron transistor design," IEDM Tech. Dig., pp. 247-250, 2000.
2. H. S. Yang et al., "Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing", IEDM Tech. Dig., pp. 1075-1077, 2004.
3. X. Chen et al., "Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond," Symp. VLSI Tech. Dig., pp. 60-61, 2006.