Concurrent CS: Preparing students for a multicore world

Proceedings of the Conference on Integrating Technology into Computer Science Education, ITiCSE

Volumn , Issue , 2008, Pages 230-234

  Ernst, Daniel J ^a   Stevenson, Daniel E ^a  

^a UNIVERSITY OF WISCONSIN EAU CLAIRE   (United States)

Author keywords

Curriculum design; Parallel programming

Indexed keywords

COMPUTER SYSTEMS; COMPUTERS; CURRICULA; INNOVATION; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PARALLEL PROGRAMMING; STUDENTS; UNMANNED AERIAL VEHICLES (UAV);

BUSINESS LEADERS; CONCURRENT PROGRAMMINGS; CURRENT TRENDS; CURRICULUM DESIGN; MICROPROCESSOR DESIGNS; MULTICORE; PROGRAMMING MODELS; PROGRAMMING PROCESSES; SHARED MEMORY MULTIPROCESSOR SYSTEMS; SKILL SETS; SOFTWARE DEVELOPMENTS; TRADITIONAL MATERIALS; UNIPROCESSOR; UNIVERSITY OF WISCONSIN;

EDUCATION COMPUTING;

EID: 57349197127     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1384271.1384333     Document Type: Conference Paper

References (6)

1. th Annual International Symposium on Computer Architecture (ISCA), 2000.
2. Krste Asanovic et al. The Landscape of Parallel Computing Research: A View from Berkeley. Electrical Engineering and Computer Sciences, University of California, Berkeley. Technical Report No. UCB/EECS-2006-183, Dec. 18, 2006; www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-183.html.
3. David E. Culler and Jaswinder Pal Singh. Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann Publishers, Inc., 1999.
4. D Geer. "Chip makers turn to multicore processors". IEEE Computer 38, 5, May 2005.
5. th SIGCSE Technical Symposium on Computer Science Education, 2005.
6. Sriram Vangal et al. "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS." Appears in the Proceedings of the 2007 International Solid State Circuits Conference (ISSCC), 2007.