SCOPUS 정보 검색 플랫폼

Microelectronic Engineering

Volumn 85, Issue 12, 2008, Pages 2403-2405

Silicon nanowire NVM cell using high-k dielectric charge storage layer

(6) Zhu, X a,b Yang, Y a Li, Q a,b Ioannou, D E a Suehle, J S b Richter, C A b

a GEORGE MASON UNIVERSITY (United States)

b NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY (United States)

Author keywords

Hafnium oxide; Non volatile memory; Self alignment; Silicon nanowire

Indexed keywords

ALIGNMENT; DATA STORAGE EQUIPMENT; GATE DIELECTRICS; GATES (TRANSISTOR); HAFNIUM; HAFNIUM COMPOUNDS; NANOSTRUCTURED MATERIALS; NANOSTRUCTURES; NANOWIRES; SILICON; SILICON COMPOUNDS; SILICON WAFERS;

AND GATES; BLOCKING LAYERS; DRY OXIDATIONS; ELECTROSTATIC CONTROLS; FABRICATION PROCESSES; HAFNIUM OXIDE; HIGH-K DIELECTRICS; NON-VOLATILE MEMORY; NVM CELLS; SELF-ALIGNMENT; SI NANOWIRES; SILICON NANOWIRE; SILICON NANOWIRES; STACKED LAYERS; TUNNELING OXIDES; VOLATILE MEMORIES;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 56649106471 PISSN: 01679317 EISSN: None Source Type: Journal
DOI: 10.1016/j.mee.2008.09.013 Document Type: Article

Times cited : (11)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.