The linear combination model for the degradation of amorphous silicon thin film transistors under drain AC stress

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 47, Issue 8 PART 1, 2008, Pages 6228-6235

  Tai, Ya Hsiang ^a   Tsai, Ming Hsien ^a   Huang, Shih Che ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

A Si:H thin film transistor (TFT); Drain stress; Reliability model

Indexed keywords

DEGRADATION; ELECTRIC FIELDS; ELECTRIC LOAD FORECASTING; ELECTROLYSIS; FORECASTING; RELIABILITY; SEMICONDUCTING SILICON COMPOUNDS; SILICON; THICK FILMS; THIN FILM DEVICES; THIN FILM TRANSISTORS; THIN FILMS; THRESHOLD VOLTAGE; TRANSISTORS;

A-SI:H TFT; A-SI:H THIN FILM TRANSISTOR (TFT); AC STRESSES; AMORPHOUS SILICON THIN FILMS; AND GATES; DEGRADATION BEHAVIORS; DEGRADATION MECHANISMS; DRAIN ELECTRODES; DRAIN STRESS; DUTY RATIOS; EXPERIMENT DATUMS; HYDROGENATED AMORPHOUS SILICONS; LINEAR COMBINATION MODELS; RELIABILITY MODEL; STRESS TIMES; VERTICAL ELECTRIC FIELDS; VOLTAGE LEVELS;

AMORPHOUS SILICON;

EID: 55149083310     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.47.6228     Document Type: Article

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