Hybrid parallelization of a compact genetic algorithm

Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003

Volumn , Issue , 2003, Pages 449-455

  Hidalgo, J I ^a   Prieto, M ^a   Lanchares, J ^a   Baraglia, R ^b   Tirado, F ^a   Garnica, O ^a  

^a UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^b CNR   (Italy)

Author keywords

Circuits; Encoding; Field programmable gate arrays; Genetic algorithms; Logic devices; Partitioning algorithms; Pins; Prototypes; Stochastic processes; Very large scale integration

Indexed keywords

ENCODING (SYMBOLS); EVOLUTIONARY ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GENETIC ALGORITHMS; LOGIC DEVICES; NETWORKS (CIRCUITS); OPTIMIZATION; POPULATION STATISTICS; RANDOM PROCESSES; VLSI CIRCUITS;

COMPACT GENETIC ALGORITHM; GENETIC ALGORITHM (GAS); GRAPH PARTITIONING PROBLEMS; HYBRID PARALLELIZATION; PARTITIONING ALGORITHMS; PINS; PROTOTYPES; STOCHASTIC OPTIMIZATIONS;

ALGORITHMS;

EID: 54849436781     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EMPDP.2003.1183624     Document Type: Conference Paper

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