Designing SOCs with Configured Cores

Designing SOCs with Configured Cores

Volumn , Issue , 2006, Pages

  Leibson, Steve ^a  

^a Tensilica Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 54249160297     PISSN: None     EISSN: None     Source Type: Book    
DOI: None     Document Type: Book

References (99)

1. Dennard R.H., Gaensslen F.H., Yu H-N., Rideout V.L., Bassous E., LeBlanc A.R. Design of ion-implanted MOSFETs with very small physical dimensions. IEEE Journal of Solid-State Circuits October 1974, 9(5):256-268.
2. Leibson S. The end of Moore's law. Embedded Systems Design December 2005, 40-47.
3. Moore G. Cramming more components onto integrated circuits. Electronics April 19, 1965, 38(8):114-117.
4. Moore G.E. "Progress in Digital Integrated Electronics," Technical Digest 1975. International Electron Devices Meeting 1975, 11-13.
5. Chang H., Cooke L., Hunt M., Martin G., McNelly A., Todd L. Surviving the SOC Revolution: A Guide to Platform-Based Design 1999, Kluwer Academic Publishers.
6. Donlin A. Transaction Level Modeling: Flows and Use Models. International Conference on Hardware/Software Codesign and System Synthesis 2004, 75-80.
7. Gries M., Keutzer K. Building ASIPS: The MESCAL Methodology 2005, Springer.
8. Keating M., Bricaud P. Reuse Methodology Manual for System-on-a-Chip Designs 1999, Kluwer Academic Publishers.
9. Leibson S., Kim J. Configurable processors: a new era in chip design. IEEE Computer July 2005, 51-59.
10. Martin G., Chang H. Winning the SOC Revolution: Experiences in Real Design 2003, Kluwer Academic Publishers.
11. Panda P.R., Dutt N., Nicolau A. Memory Issues in Embedded Systems-On-Chip 1999, Kluwer Academic Publishers.
12. Pieter van der Wolf, et al. Design and programming of embedded multiprocessors: an interface-centric approach. International Conference on Hardware/Software Codesign and System Synthesis 2004, 206-217.
13. Rowen C., Leibson S. Engineering the Complex SOC 2004, Prentice-Hall.
14. Smit G. An Energy Efficient-Reconfigurable Circuit-Switched Network-on-Chip. International SOC Conference November 2005.
15. Goes M., Keutzer K. Building ASIPS: The MESCAL Methodology 2005, Springer.
16. Xtensa LX Microprocessor Data Book 2004, Tensilica, Inc.
17. http://www.eembc.org.
18. Leibson S., Kim J. Configurable Processors: A New Era in Chip Design. IEEE Computer July 2005, 51-59.
19. Rowen C., Leibson S. Engineering the Complex SOC 2004, Prentice-Hall.
20. Xtensa 6 Microprocessor Data Book 2005, Tensilica, Inc.
21. Xtensa LX Microprocessor Data Book 2004, Tensilica, Inc.
22. Balarin E, Giusto P.D., Jurecska A., Passerone C., Sentovich E., Tabbara B., Chiodo M., Hsieh H., Lavagno L., Sangiovanni-Vincentelli A., Suzuki K. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach 1997, Kluwer Academic Publishers.
23. Chang H., Cooke L., Hunt M., Martin G., McNelly A., Todd L. Surviving the SOC Revolution: A Guide to Platform-Based Design 1999, Kluwer Academic Publishers.
24. Hellestrand G. The Engineering of Supersysterns. IEEE Computer January 2005, 103-105.
25. Kienhuis B. Deprettere, Kees Vissers, Pieter van der Wolf, "An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures,". ASAP '97: IEEE International Conference on Application-Specific Systems, Architectures and Processors 1997, 338-349.
26. Leupers R. Code Generation for Embedded Processors. 13th International Symposium on System Synthesis (ISSS'OO) 20-22 September 2000, 173-179.
27. Maestro J.A., Mozos D., Hermida R. The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. DATE'99: Proceedings of the conference on Design, automation and test in Europe 1999, 766-767.
28. Martin G., Chang H. Winning the SOC Revolution: Experiences in Real Design 2003, Kluwer Academic Publishers.
29. Marwedel P. Code generation for core processors. DAC '97: Proceedings of the 34th annual conference on Design automation 1997, 232-237.
30. Rowen C., Leibson S. Engineering the Complex SOC 2004, Prentice-Hall.
31. Xtensa LX Microprocessor Data Book 2004, Tensilica, Inc.
32. Xtensa 6 Microprocessor Data Book 2005, Tensilica, Inc.
33. Cummings C.E. Simulation and Synthesis Techniques for Asynchronous FIFO Design. Sunburst Design 2006, http://www.sunburstdesign.com.
34. Cummings C.E. Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons. Sunburst Design 2006, http://www.sunburstdesign.com.
35. Diamond Standard Processors Data Book 2006, Tensilica, Inc.
36. Leibson S., Kim J. Configurable Processors: A New Era in Chip Design. IEEE Computer July 2005, 51-59.
37. Rowen C., Leibson S. Engineering the Complex SOC 2004, Prentice-Hall.
38. Diamond Standard Processors Data Book 2006, Tensilica, Inc.
39. Leibson S., Kim J. Configurable processors: a new era in chip design. IEEE Computer July 2005, 51-59.
40. Rowen C., Leibson S. Engineering the Complex SOC 2004, Prentice-Hall.
41. Diamond Standard Processors Data Book 2006, Tensilica, Inc.
42. Leibson S., Kim J. Configurable Processors: A New Era in Chip Design. IEEE Computer July 2005, 51-59.
43. Rowen C., Leibson S. Engineering the Complex SOC 2004, Prentice-Hall.
44. Diamond Standard Processors Data Book 2006, Tensilica, Inc.
45. Kontothanassis L.I., Scott M.L. High performance software coherence for current and future architectures. Journal of Parallel and Distributed Computing September 1995, 29(2):179-195.
46. Leibson S., Kim J. Configurable Processors: A New Era in Chip Design. IEEE Computer July 2005, 51-59.
47. Rowen C., Leibson S. Engineering the Complex SOC 2004, Prentice-Hall.
48. Xtensa Microprocessor Programmer's Guide 2005, Tensilica, Inc.
49. Diamond Standard Processors Data Book 2006, Tensilica, Inc.
50. Fisher A.L., Kung H.T., Monier L., Dohi Y Architecture of the PSC: A Programmable Systolic Chip. Proceedings of the 10th International Symposium on Computer Architecture 1991, 48-53. ISCA 1983.
51. Johnson M. Superscalar Microprocessor Design 1991, Prentice-Hall.
52. Koren I., Mendelson B., Peled I., Silberman G.M. A data-driven VLSI array for arbitrary algorithms. IEEE Computer October 1988, 21(10):30-43.
53. Leibson S., Kim J. Configurable Processors: A New Era in Chip Design. IEEE Computer July 2005, 51-59.
54. Rowen C., Leibson S. Engineering the Complex SOC 2004, Prentice-Hall.
55. Xtensa Microprocessor Programmer's Guide 2005, Tensilica, Inc.
56. Diamond Standard Processors Data Book 2006, Tensilica, Inc.
57. Kennedy R., Leibson S. Audio Gets Configurable Processor http://www.audiodesignline.com.
58. Leibson S., Kim J. Configurable Processors: A New Era in Chip Design. IEEE Computer July 2005, 51-59.
59. Rowen C., Leibson S. Engineering the Complex SOC 2004, Prentice-Hall.
60. Xtensa Microprocessor Programmers Guide 2005, Tensilica, Inc.
61. Diamond Standard Processors Data Book 2006, Tensilica, Inc.
62. Leibson S., Kim J. Configurable Processors: A New Era in Chip Design. IEEE Computer July 2005, 51-59.
63. Rowen C., Leibson S. Engineering the Complex SOC 2004, Prentice-Hall.
64. Xtensa Microprocessor Programmer's Guide 2005, Tensilica, Inc.
65. Staff of Berkeley Design Technology, Inc An Independent Analysis of the Tensilica LX Processor with Vectra IX http://www.bdti.com.
66. TM: A Summary Measure of Signal Processing Speed 2005, http://www.bdti.com.
67. Furber S. Future Trends in SOC Interconnect. SOC 2005 November 15-17, 2005.
68. Ganssle J. Subtract Software Costs by Adding CPUs" Embedded Systems Design 2005, 16-25. http://www.embedded.com/showArticle.jhtmlParticleID161600589.
69. Greiner A. Distributed Micronetwork for GALS. SOC 2005 November 15-17, 2005.
70. http://www.public.itrs.net.
71. Lee S.-J. Realization of an On-chip Network for Practical Application to System-on-Chip-A Chip Designer's View. SOC 2005 November 15-17, 2005.
72. Leibson S. NOC, NOC, NOCing on heavens door: Beyond MPSOCs: A report from the seventh-annual International Symposium on System-on-Chip design December 8, 2005, EDN. http://www.edn.com/article/CA6289284.html.
73. Nurmi J. Network-on Chip: A New Paradigm for System-on-Chip Design. SOC 2005 November 15-17, 2005.
74. Smit G. An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip. SOC 2005 November 15-17, 2005.
75. A Quick Guide to High-Speed I/O for SOC Function Blocks 2006, http://www.tensilica.com.
76. Configurable Processors: What, Why, How? 2006, http://www.tensilica.com.
77. FLIX: Fast Relief for Performance-Hungry Applications 2006, http://www.tensilica.com.
78. Increasing Computational Performance Through FLIX (Flexible Length Instruction Extensions) 2006, http://www.tensilica.com.
79. Queue- and Wire-based Input and Output Ports Allow Processors to Achieve RTL-Like I/O Speeds on SOCs 2006, http://www.tensilica.com.
80. Rowen C Low Power is the New "Killer App". Globalpress 2006 2006.
81. Rowen C., Leibson S. Engineering the Complex SOC 2004, Prentice-Hall.
82. Think Outside the Bus: High-Speed I/O Alternatives for Inter-Processor Communications on SOCs 2006, http://www.tensilica.com.
83. Xtensa LX Microprocessor Data Book 2004, Tensilica, Inc. http://www.tensilica.com.
84. Xtensa 6 Microprocessor Data Book 2005, Tensilica, Inc. http://www.tensilica.com.
85. Annaratone M., Arnould E., Gross T, Kung H.T., Lam M., Menzilcioglu O. Warp Architecture and Implementation. Proceedings of the 13 th Annual Symposium on Computer Architecture June 1986, 46-356.
86. RAMP: Research Accelerator for Multiple Processors-A Community Vision for a Shared Experimental Parallel HW/SW Platform. RAMP: Research Accelerator for Multiple Processors-A Community Vision for a Shared Experimental Parallel HW/SW Platform 2005, Technical Report UCB/CSD-05-1412.
87. Brooks F.P. The Mythical Man-Month: Essays on Software Engineering, 20th Anniversary Edition 1995, Addison-Wesley.
88. Ganssle J. Subtract software costs by adding CPUs. Embedded Systems Design May 2005, 16-25.
89. International Technology Roadmap for Semiconductors: 2005 2006, http://www.public.itrs.net.
90. Johnson R.C. Defects dodged at nanoscale. Electronic Engineering Times 2006, 42.
91. Kung H.T. Why Systolic Architectures?. IEEE Computer January 1982, 37-45.
92. Lam M.S. A Systolic Array Optimizing Compiler 1989, Kluwer Academic Publishers.
93. Martin G. The Future of High-Level Modelling and System Level Design: Some Possible Methodology Scenarios. Electronic Design Process Workshop April 2002, Session 1.1.
94. Martin G. The Reality of System Design Today: Do Theory and Practice Meet?. Proceedings of the Third International Conference on Application of Concurrency to System Design (ACSD'03) 2006, 3.
95. http://www.matsuobridge.co.jp/english/bridges/index.shtm.
96. Peterson C., Sutton J., Wiley P. iWarp: A 100-MOPS, LIW Microprocessor for Multicomputers. IEEE Micro June 1991, 26-87.
97. Rhines W.C. Design in the Nanometer Age 2006, keynote speech, Dvcon.
98. Smith G. The Crisis of Complexity. Gartner Dataquest presentation, DAC 2003 2003.
99. Young H.S. Scientists develop 3 nanometer transistors March 15, 2006, Korea Herald. http://www.koreaherald.co.kr.