TMR-logic-based LUT for quickly wake-up FPGA

Midwest Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 326-329

  Suzuki, Daisuke ^a   Endoh, Tetsuo ^b   Hanyu, Takahiro ^a  

^a Laboratory for Brainware Systems

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGNS; CIRCUIT IMPLEMENTATIONS; CIRCUIT STRUCTURES; CUT OFFS; DYNAMIC CURRENTS; DYNAMIC POWER DISSIPATIONS; EXTERNAL INPUTS; EXTERNAL-; LOGIC FUNCTIONS; LOGIC NETWORKS; MOS TRANSISTORS; NONVOLATILE MEMORIES; PARALLEL CONNECTIONS; POWER DISSIPATIONS; POWER SUPPLIES; POWER-AWARE; STANDBY MODES; SWITCHING DELAYS; TMR DEVICES; VARIABLE RESISTORS;

ELECTRIC CONNECTORS; ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT MANUFACTURE; MOS DEVICES; NETWORK PROTOCOLS; NETWORKS (CIRCUITS); SENSOR NETWORKS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSISTORS;

LOGIC CIRCUITS;

EID: 54249152914     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2008.4616802     Document Type: Conference Paper

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