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Volumn , Issue , 2008, Pages 17-20

Reliability study of single-poly floating gates in 0.13 μm CMOS for use in field programmable analog arrays

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; HYBRID COMPUTERS; RELIABILITY;

EID: 54249118321     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2008.4616725     Document Type: Conference Paper
Times cited : (1)

References (11)
  • 1
    • 0035047219 scopus 로고    scopus 로고
    • P. Hasler and T. Lande, Overview of floating-gate devices, circuits, and systems. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, 48, no. 1, pp. 1-3, 2001.
    • P. Hasler and T. Lande, "Overview of floating-gate devices, circuits, and systems." Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 48, no. 1, pp. 1-3, 2001.
  • 6
    • 84943130890 scopus 로고
    • A single poly EEPROM cell structure for use in standard CMOS processes
    • K. Ohsaki, N. Asamoto, and S. Takagaki, "A single poly EEPROM cell structure for use in standard CMOS processes," IEEE Journal of Solid-State Circuits, vol. 29, no. 3, pp. 311-316, 1994.
    • (1994) IEEE Journal of Solid-State Circuits , vol.29 , Issue.3 , pp. 311-316
    • Ohsaki, K.1    Asamoto, N.2    Takagaki, S.3
  • 8
    • 0036475502 scopus 로고    scopus 로고
    • A new compact DC model of floating gate memory cells without capacitive coupling coefficients
    • L. Larcher, P. Pavan, S. Pietri, L. Albani, and A. Marmiroli, "A new compact DC model of floating gate memory cells without capacitive coupling coefficients," IEEE Transactions on Electron Devices, vol. 49, no. 2, pp. 301-307, 2002.
    • (2002) IEEE Transactions on Electron Devices , vol.49 , Issue.2 , pp. 301-307
    • Larcher, L.1    Pavan, P.2    Pietri, S.3    Albani, L.4    Marmiroli, A.5
  • 9
    • 0024910918 scopus 로고
    • Trimming analog circuits using floating-gate analog MOS memory
    • L. Carley, "Trimming analog circuits using floating-gate analog MOS memory," IEEE Journal of Solid-State Circuits, vol. 24, no. 6, pp. 1569-1575, 1989.
    • (1989) IEEE Journal of Solid-State Circuits , vol.24 , Issue.6 , pp. 1569-1575
    • Carley, L.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.