-
1
-
-
0035043074
-
Programming floating-gate circuits with UV-activated conductances
-
Jan.
-
Y. Berg, T. S. Lande, and O. Naess, “Programming floating-gate circuits with UV-activated conductances,” IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process., vol. 48, no. 1, pp. 12–19, Jan. 2001.
-
(2001)
IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process.
, vol.48
, Issue.1
, pp. 12-19
-
-
Berg, Y.1
Lande, T.S.2
Naess, O.3
-
2
-
-
0035043036
-
Multiple-input translinear element networks
-
Jan.
-
B. A. Minch, P. Hasler, and C. Diorio, “Multiple-input translinear element networks,” IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process., vol. 48, no. 1, pp. 20–28, Jan. 2001.
-
(2001)
IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process.
, vol.48
, Issue.1
, pp. 20-28
-
-
Minch, B.A.1
Hasler, P.2
Diorio, C.3
-
3
-
-
4644311036
-
Design of voltage-mode and current-mode computational circuits using floating-gate MOS transistors
-
Feb.
-
S. Vlassis and S. Siskos, “Design of voltage-mode and current-mode computational circuits using floating-gate MOS transistors,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 2, pp. 329–341, Feb. 2004.
-
(2004)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.51
, Issue.2
, pp. 329-341
-
-
Vlassis, S.1
Siskos, S.2
-
4
-
-
0033681591
-
Calibration and matching of floating-gate devices
-
May 28-31
-
W. P. Millard, Z. K. Kalyjian, and A. G. Andreou, “Calibration and matching of floating-gate devices,” in Proc. 2000 IEEE Int. Symp. Circuits Syst., May 28-31, 2000, vol. 4, pp. 389–392.
-
(2000)
Proc. 2000 IEEE Int. Symp. Circuits Syst.
, vol.4
, pp. 389-392
-
-
Millard, W.P.1
Kalyjian, Z.K.2
Andreou, A.G.3
-
5
-
-
4344674098
-
Comparison of quasi-/pseudo-floating-gate techniques
-
May 23-26
-
I. Seo and R. M. Fox, “Comparison of quasi-/pseudo-floating-gate techniques,” in Proc. 2004 IEEE Int. Symp. Circuits Syst., May 23-26, 2004, vol. 1, pp. 1-365–1-368.
-
(2004)
Proc. 2004 IEEE Int. Symp. Circuits Syst.
, vol.1
, pp. 1-365-1-368
-
-
Seo, I.1
Fox, R.M.2
-
6
-
-
0141973749
-
Solution to trapped charge in FGMOS transistors
-
Sep.
-
E. Rodriguez-Villegas and H. Barnes, “Solution to trapped charge in FGMOS transistors,” Electron. Lett., vol. 39, no. 19, pp. 1416–1417, Sep. 18, 2003.
-
(2003)
Electron. Lett.
, vol.39
, Issue.19
, pp. 1416-1417
-
-
Rodriguez-Villegas, E.1
Barnes, H.2
-
7
-
-
0742321273
-
A 1-V micropower log-domain integrator based on FGMOS transistors operating in weak inversion
-
Jan.
-
E. Rodriguez-Villegas, A. Yufera, and A. Rueda, “A 1-V micropower log-domain integrator based on FGMOS transistors operating in weak inversion,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 256–259, Jan. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.1
, pp. 256-259
-
-
Rodriguez-Villegas, E.1
Yufera, A.2
Rueda, A.3
-
8
-
-
0242473166
-
Phenomenological theory to model leakage currents in metal-insulator-metal capacitor systems
-
R. Ramprasad, “Phenomenological theory to model leakage currents in metal-insulator-metal capacitor systems,” Phys. Status Solidi (B), Appl. Res., vol. 239, no. 1, pp. 59–70.
-
Phys. Status Solidi (B), Appl. Res.
, vol.239
, Issue.1
, pp. 59-70
-
-
Ramprasad, R.1
-
9
-
-
0025507283
-
Neuromorphic electronic systems
-
Oct.
-
C. Mead, “Neuromorphic electronic systems,” Proc. IEEE, vol. 78, no. 10, pp. 1629–1636, Oct. 1990.
-
(1990)
Proc. IEEE
, vol.78
, Issue.10
, pp. 1629-1636
-
-
Mead, C.1
-
10
-
-
25844469564
-
Floating-gate circuits and systems
-
C. Toumazou, G. Moschytz, and B. Gilbert, Eds. Dordrecht, The Netherlands: Kluwer
-
T. S. Lande, “Floating-gate circuits and systems,” in Trade-Offs in Analog Circuit Design, C. Toumazou, G. Moschytz, and B. Gilbert, Eds. Dordrecht, The Netherlands: Kluwer, 2002, pp. 115–137.
-
(2002)
Trade-Offs in Analog Circuit Design
, pp. 115-137
-
-
Lande, T.S.1
-
11
-
-
33644651482
-
A precision CMOS amplifier using floating-gates for offset cancellation
-
Sep.
-
V. Srinivasan, G. J. Serrano, J. Gray, and P. Hasler, “A precision CMOS amplifier using floating-gates for offset cancellation,” in Proc. CICC'05, Sep. 18–21, 2005, pp. 739–742.
-
(2005)
Proc. CICC'05
, pp. 18-21
-
-
Srinivasan, V.1
Serrano, G.J.2
Gray, J.3
Hasler, P.4
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