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Volumn , Issue , 2008, Pages 617-620

Trapped charge characterization and removal on Floating-gate transistors

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL FACTORS; FLOATING GATES; GATE TRANSISTORS; METAL CONTACTS; METAL FLOWS; TRAPPED CHARGES;

EID: 54249086281     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2008.4616875     Document Type: Conference Paper
Times cited : (3)

References (7)
  • 2
    • 0141973749 scopus 로고    scopus 로고
    • Solution to trapped charge in fgmos transistors
    • September
    • E. Rodriguez-Villegas and H. Barnes, "Solution to trapped charge in fgmos transistors." Electronics Letters, vol. 39, no. 19, pp. 1416 - 1417, September 2003.
    • (2003) Electronics Letters , vol.39 , Issue.19 , pp. 1416-1417
    • Rodriguez-Villegas, E.1    Barnes, H.2
  • 4
    • 33746394242 scopus 로고    scopus 로고
    • I. StJohn and RM Fox, Leakage effects in metal-connected floating-gate circuits, Circuits and Systems II: Express Briefs, IEEE Transactions on [see also Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on], 53, no. 7, pp. 577-579, 2006.
    • I. StJohn and RM Fox, "Leakage effects in metal-connected floating-gate circuits, " Circuits and Systems II: Express Briefs, IEEE Transactions on [see also Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on], vol. 53, no. 7, pp. 577-579, 2006.
  • 5
    • 54249134511 scopus 로고    scopus 로고
    • H. Ishiii T. Shibata, H. Kosaka and T. Ohmi, A functional mos transistor featuring gate-level weighted sum and thresh-old operations, Solid-State Circuits, IEEE Journal of, 30, no. 8, pp. 913 - 922, 1995.
    • H. Ishiii T. Shibata, H. Kosaka and T. Ohmi, "A functional mos transistor featuring gate-level weighted sum and thresh-old operations, " Solid-State Circuits, IEEE Journal of, vol. 30, no. 8, pp. 913 - 922, 1995.
  • 6
    • 20444492464 scopus 로고    scopus 로고
    • Peter R. Kinget, Device mismatch and tradeoffs in the design of analog circuits, Solid-State Circuits, IEEE Journal of, 40, no. 6, pp. 1212-1224, June 2005.
    • Peter R. Kinget, "Device mismatch and tradeoffs in the design of analog circuits, " Solid-State Circuits, IEEE Journal of, vol. 40, no. 6, pp. 1212-1224, June 2005.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.