Accelerator architectures

IEEE Micro

Volumn 28, Issue 4, 2008, Pages 4-12

  Patel, Sanjay ^a   Hwu, Wen Mei W ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Accelerator architectures; Special issues and sections

Indexed keywords

EID: 53749108455     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2008.50     Document Type: Editorial

References (11)

1. M. Hummel, M. Krause, and D. O'Flaherty, "AMD and HP: Protocol Enhancements for Tightly Coupled Accelerators," white paper, AMD, 2007; http://www.hp.com/techservers/hpccn/hpccollaboration/ADCatalyst/ downloads/AMD_HPTCAWP.pdf.
2. I. Gelado et al., "CUBA: An Architecture for Efficient CPU/Co-processor Data Communication," Proc. 22nd Ann. Intl Conf. Supercomputing (ICS 08), ACM Press, pp. 299-308.
3. J. Stratton, S. Stone, and W.-m. Hwu, "MCUDA: An Efficient Implementation of CUDA Kernels on Multi-cores," tech. report IMPACT-08-01, Univ. of Illinois at Urbana-Champaign, 2008.
4. K. Fatahalian et al., "Sequoia: Programming the Memory Hierarchy," Proc. 2006 ACM/IEEE Conf. Supercomputing (SC 06), ACM Press, 2006; http://doi.acm.org/l0.1145/1188455.1188543.
5. M. Puschel et al., "SPIRAL: Code Generation for DSP Transforms," Proc. IEEE, vol. 93, no. 2, Feb. 2005, pp. 232-275.
6. S. Ryoo et al., "Optimization Principles and Application Performance Evaluation of a Multithreaded GPU Using CUDA," Proc. 13th ACM SIGPLAN Symp. Principles and Practice of Parallel Programming (PPoPP 08), ACM Press, 2008, pp. 73-82.
7. U. Kapasi et al., "The Imagine Stream Processor," Proc. 2002 IEEE Int'l Conf. Computer Design (ICCD 02), IEEE CS Press, 2002, pp. 282-288.
8. M.B. Taylor et al., "The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs," IEEE Micro, vol. 22, no. 2, Mar./Apr. 2002, pp. 25-35.
9. J. Held, J. Bautista, and S. Koehl, "From a Few Cores to Many: A Tera-scale Computing Research Overview," white paper, Intel, 2006; ftp://download.intel.com/research/platform/terascale/ terascale_overview_paper.pdf.
10. Z. Yu et al., "An Asynchronous Array of Simple Processors for DSP Applications," IEEE Int'l Solid-State Circuits Conference (ISSCC 06), IEEE Press, 2006, pp. 428-429.
11. J. Kelm et al., "Rigel: A Scalable Processor Architecture for 1000+ Core Computing," tech. report IMPACT-08-02, Univ. of Illinois at Urbana-Champaign, 2008.