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Volumn , Issue , 1998, Pages 7-14

Design of fault-secure parity-prediction Booth multipliers

Author keywords

[No Author keywords available]

Indexed keywords

BOOTH MULTIPLIERS; FAULT SECURE; PARITY PREDICTION; RECODING; SINGLE FAULT;

EID: 53749095643     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655830     Document Type: Conference Paper
Times cited : (7)

References (16)
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  • 4
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    • The powerpc™ 603 microprocessor: A high performance, low power, superscalar risc microprocessor
    • B. Burgess, M. Alexander. Y.-W. Ho. S.P. Litch, and Cols., "The PowerPC™ 603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor, Design Automation Conference DAC94, pp. 330-306,1994
    • (1994) Design Automation Conference DAC94 , pp. 330-306
    • Burgess, B.1    Alexander, M.2    Ho, Y.-W.3    Litch, S.P.4
  • 5
    • 0001305152 scopus 로고
    • Design of dynamically checked computers
    • Scotland. Aug.
    • W.C. Carter, P.R. Schneider, "Design of Dynamically Checked Computers", in Proc. IFIPConi.Edinburqh. Scotland. Aug. 1968,pp.878-883
    • (1968) Proc. IFIPConi.Edinburqh , pp. 878-883
    • Carter, W.C.1    Schneider, P.R.2
  • 6
    • 0347391902 scopus 로고    scopus 로고
    • A cad framework for efficient self-checking data path design
    • Aghia Pelaghia, Crete, Greece, July
    • Duarte R. O, Nicolaidis M., "A CAD Framework for Efficient Self-Checking Data Path Design", 3rd IEEE Intl. On-Line Testing Workshop, Aghia Pelaghia, Crete, Greece, July 1997.
    • (1997) 3rd IEEE Intl. On-Line Testing Workshop
    • Duarte, R.O.1    Nicolaidis, M.2
  • 8
    • 84937349985 scopus 로고
    • High spaed arithmetic in binary computers
    • lam iarv
    • O.L McSorley, "High Spaed Arithmetic in Binary Computers", in Proc. of the IRE, pp. 67-91.lam iarv 1 961
    • (1961) Proc. of the IRE , pp. 67-91
    • McSorley, O.L.1
  • 9
    • 0026136710 scopus 로고
    • A 10-ns 54x54 paral elstructuredcfull array multiplier with 0.5pm cmos technology
    • April
    • J, Mori, M. Nagamatsu, Wh. S.H"anaka, M. Noda-et at., "A 10-ns 54x54 Paral elStructuredcFull Array Multiplier with 0.5pm CMOS Technology, IEEE Journal of Solid-State Circuits, vol. SC-26 N4, pp. 600-605, April 1991
    • (1991) IEEE Journal of Solid-State Circuits , vol.SC-26 , Issue.4 , pp. 600-605
    • Mori, J.1    Nagamatsu, M.2    Hanaka, S.3    Noda, M.4
  • 10
    • 0027844138 scopus 로고
    • Efficient implementation of self-checking adders and alus
    • Toulouse France, June
    • Nicolaidis M. Efficient Implementation of Self-Checking Adders and ALUs. Proc. 23th Fault Tolerant Computing Symposium, Toulouse France, June 1993.
    • (1993) Proc. 23th Fault Tolerant Computing Symposium
    • Nicolaidis, M.1
  • 12
    • 84893760947 scopus 로고
    • A regularly structured 54-bit modified wallace-tree multiplier
    • T. Sato, N. Nakajima, T. Sukemura, G. Goto, "A Regularly Structured 54-Bit Modified Wallace-tree Multiplier". VLSBesign Conference, pp. 1.1/! Ca," 1981
    • (1981) VLSBesign Conference , pp. 11
    • Sato, T.1    Nakajima, N.2    Sukemura, T.3    Goto, G.4
  • 14
    • 0011904242 scopus 로고
    • Performance/Area tradeoffs in booth multipliers
    • November
    • H. Al-Twaijry and M. Fli/nn, "Performance/Area Tradeoffs in Booth Multipliers". Tech". Rep.: CSL-TR-95-684, November 1995
    • (1995) Tech Rep.: CSL-TR-95-684
    • Al-Twaijry, H.1    Flinn, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.