An automated runtime power-gating scheme

2007 IEEE International Conference on Computer Design, ICCD 2007

Volumn , Issue , 2007, Pages 382-387

  Hamada, Mototsugu ^a   Kitahara, Takeshi ^a   Kawabe, Naoyuki ^a   Sato, Hironori ^a   Nishikawa, Tsuyoshi ^a   Shimazawa, Takayoshi ^a   Yamashita, Takahiro ^a   Hara, Hiroyuki ^a   Oowaki, Yukihito ^a   Furusawa, Toshiyuki ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE MODE; AREA OVERHEAD; CLOCK-GATING; CMOS DESIGN; COMPUTER DESIGNS; CONTROL SIGNALLING; INTERNATIONAL CONFERENCES; LEAKAGE POWER; POWER SAVINGS; POWER-GATING; RUN-TIME; SLEEP MODES; SYSTEM OPERATIONS;

FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; SLEEP RESEARCH;

ENERGY CONSERVATION;

EID: 52949105135     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2007.4601928     Document Type: Conference Paper

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