Segmented Digital Clock Manager- FPGA based digital pulse width modulator technique

PESC Record - IEEE Annual Power Electronics Specialists Conference

Volumn , Issue , 2008, Pages 3036-3042

  Batarseh, Majd G ^a   Al Hoor, Wisam ^a   Huang, Lilly ^b   Iannello, Chris ^a   Batarseh, Issa ^a  

^a UNIVERSITY OF CENTRAL FLORIDA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; ELECTRIC CONVERTERS; MANAGERS; MODULATION; POWER ELECTRONICS; PULSE WIDTH MODULATION; SYSTEMS ANALYSIS;

DIGITAL CLOCK MANAGER; DIGITAL MODULATORS; DIGITAL PULSES; DUTY CYCLES; FIELD PROGRAMMABLE GATE ARRAY; FPGA BOARDS; FREQUENCY OPERATION; LOW POWERS; PHASE SHIFTING; PROPOSED ARCHITECTURES;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 52349099555     PISSN: 02759306     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PESC.2008.4592415     Document Type: Conference Paper

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