Physical investigation of the impact of electrolessly deposited self-aligned caps on insulation of copper interconnects

Microelectronic Engineering

Volumn 85, Issue 10, 2008, Pages 2051-2054

  Olivier, S ^a   Decorps, T ^b   Bernard, M ^a   Haumesser, P H ^a   Passemard, G ^b  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

Copper interconnects; CoWP; Electroless deposition; Process selectivity; Self aligned barriers

Indexed keywords

COPPER; CURRENT DENSITY; ELECTROLESS PLATING; OPTICAL INTERCONNECTS;

COPPER INTERCONNECTS; COWP; ELECTROLESS DEPOSITION; PROCESS SELECTIVITY; SELF-ALIGNED; SELF-ALIGNED BARRIERS;

ULSI CIRCUITS;

EID: 52149096266     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2008.04.015     Document Type: Article

References (3)

1. Decorps T., Haumesser P.H., Olivier S., Roule A., Joulaud M., Pollet O., Avale X., and Passemard G. Microelectronic Engineering 83 (2006) 2082-2087
2. Gambino J., Wynne J., Gill J., Mongeon S., Meatyard D., Lee B., Bamnolker H., Hall L., Li N., Hernandez M., et al. Microelectronic Engineering 83 (2006) 2059-2067
3. S. Olivier, T. Decorps, P.H. Haumesser, G. Passemard, X. Avale, M. Joulaud, O. Pollet, in: Proceedings of the Electrochemical Society Conference, Cancun, Mexico, November 2006.