A 40GHz fractional-N frequency synthesizer in 0.13 μ CMOS

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

Volumn , Issue , 2008, Pages 295-298

  Hung, Chao Ching ^a   Shen, Ding Shiuan ^a   Liu, Shen Luan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELTA SIGMA MODULATION; DIGITAL INTEGRATED CIRCUITS; DISPLAY DEVICES; ELECTRONICS INDUSTRY; FREQUENCY SYNTHESIZERS; MODULATORS; OPTICAL DESIGN; RADIO WAVES; SIGNAL GENERATORS;

CMOS PROCESSING; DELTA-SIGMA; DIE AREA; FRACTIONAL-N FREQUENCY SYNTHESIZER; FREQUENCY RESOLUTIONS; MULTI-MODULUS; PHASE-NOISE; RADIO FREQUENCY INTEGRATED CIRCUITS; SECOND ORDERS;

INTEGRATED CIRCUITS;

EID: 52149095420     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RFIC.2008.4561439     Document Type: Conference Paper

References (6)

1. M. Tiebout et al, "A folly Integrated 13GHz AE Fractional-N PLL in 0.13um CMOS," IEEE International Solid-State Circuit Conference, Feb. 2004
2. J. Craninckx and M.S.J. Steyaert, "A 1.75GHz/3V Dual-Modulus Divide by 128/129 Prescaler in 0.7μm CMOS," IEEE J. Solid-State Circuits, pp. 890 -897, July 1996.
3. Y. Ding and K.K. O, "A 21-GHz fractional-N synthesizer in 130-nm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, session 25-3, 2007.
4. C. S. Vaucher et al., "A family of low-power truly modular programmable dividers in standard 0.35um CMOS technology," IEEE J. Solid-State Circuits, vol. 35, NO.7, pp. 1039-1045, July 2000.
5. T. C. Lee and Y. C. Huang, " The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application," IEEE J. Solid-State Circuits, vol. 41.NO.6, pp. 1253-1261, July 2006.
6. B. Razavi, Design of Integrated Circuits for Optical communications, New York: McGraw-Hill, 2003.