SRAM cell design protected from SEU upsets

Proceedings - 14th IEEE International On-Line Testing Symposium, IOLTS 2008

Volumn , Issue , 2008, Pages 169-170

  Shiyanovskii, Yuriy ^a   Wolff, Francis ^a   Papachristou, Chris ^a  

^a CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AND RECOVERY; AREA OVERHEAD; BROKEN DOWN; CRITICAL CHARGES; CURRENT MONITORS; ERROR-CORRECTING CODES; MEMORY PROTECTION; NEW DESIGN; ON-LINE TESTING; PROTECTION LEVEL; PROTECTION METHODS; SOFT ERRORS; SRAM CELLS; TIME BEHAVIOR;

CAPACITANCE; CAPACITORS; CELLS; CMOS INTEGRATED CIRCUITS; CYTOLOGY; DIELECTRIC DEVICES; ELECTRIC BREAKDOWN; ELECTRIC CURRENTS; ELECTRIC EQUIPMENT; ELECTRIC NETWORK ANALYSIS; ENERGY STORAGE; ERROR ANALYSIS; HARDENING; MICROPROCESSOR CHIPS; STANDARDS; SUBMARINE PIPELINES; URANIUM POWDER METALLURGY;

STATIC RANDOM ACCESS STORAGE;

EID: 52049112062     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2008.49     Document Type: Conference Paper

References (8)

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