A fully integrated 48-GHz low-noise PLL with a constant loop bandwidth

2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systms - Digest of Papers, SiRF

Volumn , Issue , 2008, Pages 82-85

  Herzel, Frank ^a   Glisic, Srdjan ^a   Osmany, Sabbir A ^a   Scheytt, J Christoph ^a   Schmalz, Klaus ^a   Winkler, Wolfgang ^a   Engels, Michael ^b  

^a IHP   (Germany)

^b IMST GMBH   (Germany)

Author keywords

60 GHz; BiCMOS; Dual loop PLL; Frequency synthesizer; Silicon germanium

Indexed keywords

BICMOS TECHNOLOGY; CMOS INTEGRATED CIRCUITS; ELECTRONICS INDUSTRY; FREQUENCY SYNTHESIZERS; INTEGRATED CIRCUITS; NONMETALS; PHASE LOCKED LOOPS; PUMPS; RADIOFREQUENCY SPECTROSCOPY; SEMICONDUCTING SILICON; SIGNAL GENERATORS; SILICON; TELECOMMUNICATION SYSTEMS;

60 GHZ; BICMOS; CHARGE PUMPING; DUAL-LOOP PLL; FREQUENCY SYNTHESIZER; FULLY INTEGRATED; LOOP BAND WIDTH; LOOP DYNAMICS; LOW-NOISE; OUTPUT VOLTAGES; PLL ARCHITECTURE; RF SYSTEMS; SIGE BICMOS TECHNOLOGY; SILICON-GERMANIUM; WIRELESS TRANSCEIVERS;

MONOLITHIC INTEGRATED CIRCUITS;

EID: 52049094381     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SMIC.2008.27     Document Type: Conference Paper

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