Circuit performance characterization of digital 45-nm CMOS technology for applications around 110 GHz

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 162-163

  Aroca, R A ^a   Tomkins, A ^a   Doi, Y ^b   Yamamoto, T ^b   Voinigescu, S P ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MICROWAVE CIRCUITS; MILLIMETER WAVES; NOISE FIGURE; TIMING CIRCUITS; VARACTORS; VLSI CIRCUITS;

CIRCUIT PERFORMANCE; CMOS TECHNOLOGY; DIGITAL CMOS; DOWN CONVERTERS; MM WAVES; MOSFETS; OPTIMAL NOISE; TEST VEHICLE;

CMOS INTEGRATED CIRCUITS;

EID: 51949102144     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585991     Document Type: Conference Paper

References (6)

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4. T.O Dickson et al., IEEE JSSC, Vol.41,pp.1830-1845,Aug. 2006.
5. K.W. Tang et al, IEEE CICC Dig., pp.749-752, Sept. 2007.
6. T. Yao et al., IEEE JSSC, Vol.42, pp.1044-1057, May 2007.