-
1
-
-
4944232720
-
A Tool for Converting Finite State Machine to VHDL
-
Niagara Falls, Ontario, Canada, May
-
A. Abdel-Hamid, M. Zaki, and S. Tahar, "A Tool for Converting Finite State Machine to VHDL", Proc. of IEEE Canadian Conference on Electrical & Computer Engineering, Niagara Falls, Ontario, Canada, Vol. 4, May 2004, pp. 1907-1910.
-
(2004)
Proc. of IEEE Canadian Conference on Electrical & Computer Engineering
, vol.4
, pp. 1907-1910
-
-
Abdel-Hamid, A.1
Zaki, M.2
Tahar, S.3
-
2
-
-
33646912488
-
A Public Key Watermarking Techniques for IP Designs
-
Munich, Germany, March
-
A.T. Abdel-Hamid, S. Tahar and E.M. Aboulhamid, "A Public Key Watermarking Techniques for IP Designs"; Proc. Design, Automation and Test in Europe, Munich, Germany, March 2005, pp. 330-335.
-
(2005)
Proc. Design, Automation and Test in Europe
, pp. 330-335
-
-
Abdel-Hamid, A.T.1
Tahar, S.2
Aboulhamid, E.M.3
-
3
-
-
0003840779
-
-
Kluwer Academic Publishers
-
H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, and L. Todd, "Surviving the SOC Revolution: A Guide to Platform-Based Design", Kluwer Academic Publishers, 1999.
-
(1999)
Surviving the SOC Revolution: A Guide to Platform-Based Design
-
-
Chang, H.1
Cooke, L.2
Hunt, M.3
Martin, G.4
McNelly, A.5
Todd, L.6
-
5
-
-
14244254664
-
On Public-key Steganography in the Presence of an Active Warden
-
Technical Report RC20931. IBM Research Division, T. J. Watson Research Center, Santa Clara, California, USA, July
-
S. Cravar, "On Public-key Steganography in the Presence of an Active Warden", Technical Report RC20931. IBM Research Division, T. J. Watson Research Center, Santa Clara, California, USA, July 1997.
-
(1997)
-
-
Cravar, S.1
-
6
-
-
0026172995
-
Test Selection Based on Finite State Models
-
June
-
S. Fujiwara, G. Bochmann, F. Khendek, M. Amalou, and A. Ghedamsi, "Test Selection Based on Finite State Models", IEEE Transactions on Software Engineering, Vol. 17, Issue 6, June 1991, pp. 591-603.
-
(1991)
IEEE Transactions on Software Engineering
, vol.17
, Issue.6
, pp. 591-603
-
-
Fujiwara, S.1
Bochmann, G.2
Khendek, F.3
Amalou, M.4
Ghedamsi, A.5
-
7
-
-
0031623974
-
Techniques for Intellectual Property Protection of DSP Designs
-
Munich, Germany
-
I. Hong and M. Potkonjak, "Techniques for Intellectual Property Protection of DSP Designs", IEEE International Conference. Acoustics, Speech, and Signal Processing, Munich, Germany, Vol. 5, 1998, pp. 3133-3136.
-
(1998)
IEEE International Conference. Acoustics, Speech, and Signal Processing
, vol.5
, pp. 3133-3136
-
-
Hong, I.1
Potkonjak, M.2
-
9
-
-
0035472848
-
Constraint-Based Watermarking Techniques for Design IP Protection
-
October
-
A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe, "Constraint-Based Watermarking Techniques for Design IP Protection", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 10, October 2001, pp. 1236-1252.
-
(2001)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.20
, Issue.10
, pp. 1236-1252
-
-
Kahng, A.B.1
Lach, J.2
Mangione-Smith, W.H.3
Mantik, S.4
Markov, I.L.5
Potkonjak, M.6
Tucker, P.7
Wang, H.8
Wolfe, G.9
-
10
-
-
33746056772
-
Cryptanalysis of UCLA Watermarking Schemes for Intellectual Property Protection
-
Information Hiding, Springer
-
T. V. Le, and Y. Desmedt, "Cryptanalysis of UCLA Watermarking Schemes for Intellectual Property Protection", In Information Hiding, Lecture Notes in Computer Science, vol. 2578, pp. 213-225, Springer 2002.
-
(2002)
Lecture Notes in Computer Science
, vol.2578
, pp. 213-225
-
-
Le, T.V.1
Desmedt, Y.2
-
11
-
-
51949096719
-
-
K. McElvain, LGSynth93 Benchmark Set: Version 4.0, 1993
-
K. McElvain, "LGSynth93 Benchmark Set: Version 4.0", http://www.cbl.ncsu.edu/pub/Benchmark dirs/LGSynth93/, 1993.
-
-
-
-
12
-
-
0034771122
-
IP Protection for VLSI Designs Via Watermarking of Routes
-
Washington, DC, USA, September
-
N. Narayan, R. D. Newbould, J. D. Carothers, J. J. Rodrguez, and W. Timothy Holman, "IP Protection for VLSI Designs Via Watermarking of Routes", Proc. 14th Annual IEEE International ASIC/SOC Conference, Washington, DC, USA, September 2001, pp. 406-410.
-
(2001)
Proc. 14th Annual IEEE International ASIC/SOC Conference
, pp. 406-410
-
-
Narayan, N.1
Newbould, R.D.2
Carothers, J.D.3
Rodrguez, J.J.4
Timothy Holman, W.5
-
13
-
-
0035440030
-
Techniques for the Creation of Digital Watermarks in Sequential Circuit Designs
-
September
-
A. L. Oliveira, "Techniques for the Creation of Digital Watermarks in Sequential Circuit Designs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 9, September 2001, pp. 1101-1117.
-
(2001)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.20
, Issue.9
, pp. 1101-1117
-
-
Oliveira, A.L.1
-
14
-
-
0032680807
-
Information Hiding- A Survey
-
July
-
F. A. P. Petitcolas, R. J. Anderson, and M. G. Kuhn, "Information Hiding- A Survey", Proceeding of the IEEE, Special Issue on the Protection of Multimedia Content, Vol. 87, No. 7, July 1999, pp. 1062-1078.
-
(1999)
Proceeding of the IEEE
, vol.87
, Issue.7
, pp. 1062-1078
-
-
Petitcolas, F.A.P.1
Anderson, R.J.2
Kuhn, M.G.3
-
16
-
-
0003934798
-
SIS: A System for Sequential Circuit Synthesis
-
Technical Report, Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, California, USA
-
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni- Vincentelli, "SIS: A System for Sequential Circuit Synthesis", Technical Report, Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, California, USA, 1992.
-
(1992)
-
-
Sentovich, E.M.1
Singh, K.J.2
Lavagno, L.3
Moon, C.4
Murgai, R.5
Saldanha, A.6
Savoj, H.7
Stephan, P.R.8
Brayton, R.K.9
Sangiovanni- Vincentelli, A.10
-
17
-
-
0033879740
-
Watermarking-Based Copyright Protection of Sequential Functions
-
February
-
I. Torunoglu, and E. Charbon, "Watermarking-Based Copyright Protection of Sequential Functions", IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, February 2000, pp.434-440.
-
(2000)
IEEE Journal of Solid-State Circuits
, vol.35
, Issue.3
, pp. 434-440
-
-
Torunoglu, I.1
Charbon, E.2
-
18
-
-
51949107643
-
-
VSI Alliance, VSI Alliance Architecture Document: Version 1.0, VSI Alliance, 1997
-
VSI Alliance, "VSI Alliance Architecture Document: Version 1.0", VSI Alliance, 1997.
-
-
-
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