-
1
-
-
1642364107
-
The Chimaera Reconfigurable Functional Unit
-
February
-
S. Hauck and T. Fry, The Chimaera Reconfigurable Functional Unit., IEEE Transactions on VLSI Systems, Vol 12, No. 2, February 2004.
-
(2004)
IEEE Transactions on VLSI Systems
, vol.12
, Issue.2
-
-
Hauck, S.1
Fry, T.2
-
2
-
-
0034187952
-
Morphosys, An Integrated Recon-figurable System for Data-Parallel and Computational Intensive Applications
-
May
-
H. Singh and G. LU, Morphosys, An Integrated Recon-figurable System for Data-Parallel and Computational Intensive Applications,. IEEE Transactions on Computers, Vol 49, No. 5, May 2000.
-
(2000)
IEEE Transactions on Computers
, vol.49
, Issue.5
-
-
Singh, H.1
LU, G.2
-
3
-
-
0034314477
-
A 1-V Heterogeneous Reconfigurable DSP IC for Wireless Baseband Digital Signal Processing
-
November
-
H. Zhang and V. Prabhu, A 1-V Heterogeneous Reconfigurable DSP IC for Wireless Baseband Digital Signal Processing,. IEEE Transactions on Solid State Circuits, Vol 35, No. 11, November 2000.
-
(2000)
IEEE Transactions on Solid State Circuits
, vol.35
, Issue.11
-
-
Zhang, H.1
Prabhu, V.2
-
4
-
-
0034996112
-
FPGA Hardware Synthesis from MATLAB™
-
IEEE
-
M. Haldar, A. Nayak, N. Shenoy, A. Choudhary and P. Banerjee FPGA Hardware Synthesis from MATLAB™,. Proceedings of the 14th International Conference on VLSI Design, IEEE 2001.
-
(2001)
Proceedings of the 14th International Conference on VLSI Design
-
-
Haldar, M.1
Nayak, A.2
Shenoy, N.3
Choudhary, A.4
Banerjee, P.5
-
5
-
-
51949118712
-
-
Xilinx Floating-Point Operator v3.0, Xilinx, Inc. Product Specification DS335, September 28, 2006.
-
"Xilinx Floating-Point Operator v3.0", Xilinx, Inc. Product Specification DS335, September 28, 2006.
-
-
-
-
6
-
-
26444479778
-
Optimization by Simulated Annealing
-
13 May
-
S. Kirkpatrick, C. D. Gelatt, Jr. M. P. Vecchi, Optimization by Simulated Annealing. Science, Volume 220, Number 4598, 13 May 1983,
-
(1983)
Science
, vol.220
, Issue.4598
-
-
Kirkpatrick, S.1
Gelatt Jr., C.D.2
Vecchi, M.P.3
-
7
-
-
51949085772
-
-
H. DeMuth, M. Beale, MATLAB Neural Network Toolbox version 4.0, The Mathworks, Inc, July, 2002
-
H. DeMuth, M. Beale, "MATLAB Neural Network Toolbox version 4.0", The Mathworks, Inc., July, 2002.
-
-
-
-
8
-
-
0040253703
-
-
Fourth Ed, Helmers Publishing
-
Palmer, R. C., The Bar Code Book: A Comprehensive Guide to Reading, Printing, Specifying and Applying Bar Code and Other Machine Readable Symbols,. Fourth Ed., Helmers Publishing, 2001.
-
(2001)
The Bar Code Book: A Comprehensive Guide to Reading, Printing, Specifying and Applying Bar Code and Other Machine Readable Symbols
-
-
Palmer, R.C.1
-
9
-
-
51949090447
-
FPGA Implementation of a Fully and Partially Connected MLP: Application to Automatic Speech Recognition
-
A. R. Omondi ans J. C. Rajapakse eds, Springer
-
A. Canas, E. M. Ortigosa, E. Ross and P. Ortigosa, FPGA Implementation of a Fully and Partially Connected MLP: Application to Automatic Speech Recognition,. FPGA Implementations of Neural Networks, 271-296, A. R. Omondi ans J. C. Rajapakse (eds). Springer 2006.
-
(2006)
FPGA Implementations of Neural Networks
, pp. 271-296
-
-
Canas, A.1
Ortigosa, E.M.2
Ross, E.3
Ortigosa, P.4
-
10
-
-
33846101011
-
The Impact of Arithmetic Representation on Implementing MLP-BP on FPGA: A Study
-
January
-
A. W. Savich, M. Moussa, S. Areibi, The Impact of Arithmetic Representation on Implementing MLP-BP on FPGA: A Study,. IEEE Transactions on Neural Networks, Vol 18, No. 1, January 2007.
-
(2007)
IEEE Transactions on Neural Networks
, vol.18
, Issue.1
-
-
Savich, A.W.1
Moussa, M.2
Areibi, S.3
-
11
-
-
34248645728
-
-
A.. Himavathi, D. Anitha, A. Muthuramalingam, Feedforward Neural Network Implementation in FPGA Using Layer Multiplexing for Effective Resource Utilization,. IEEE Transactions on Neural Networks, 18, No. 3, May 2007.
-
A.. Himavathi, D. Anitha, A. Muthuramalingam, Feedforward Neural Network Implementation in FPGA Using Layer Multiplexing for Effective Resource Utilization,. IEEE Transactions on Neural Networks, Vol 18, No. 3, May 2007.
-
-
-
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