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Volumn , Issue , 2007, Pages 115-118

Design and performance evaluation of a reconfigurable delta MIN for MPSOC

Author keywords

Delta MIN; MPSOC; Network design; NOC; Reconfigurable MIN

Indexed keywords

BIOLOGICAL MATERIALS; ELECTRIC NETWORK TOPOLOGY; FAULT TOLERANCE; INTERCONNECTION NETWORKS; MICROELECTRONICS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; QUALITY ASSURANCE; SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 51849137453     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.2007.4497674     Document Type: Conference Paper
Times cited : (14)

References (14)
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    • Cesario, W.O.1
  • 2
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    • The SP2 High-Performance Switch
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    • Stunkel, C.1
  • 4
    • 79955143971 scopus 로고    scopus 로고
    • Creating a world of smart reconfigurable devices
    • R. Lauwereins, "Creating a world of smart reconfigurable devices", In Field Programmable Logic FPL (2002), pp790-794.
    • (2002) In Field Programmable Logic FPL , pp. 790-794
    • Lauwereins, R.1
  • 5
    • 0022752120 scopus 로고
    • A simulation study of the cray x-mp memory system
    • T. Cheung, "A simulation study of the cray x-mp memory system", IEEE Transactions on Computers 35 (7) (1986), pp613-622.
    • (1986) IEEE Transactions on Computers , vol.35 , Issue.7 , pp. 613-622
    • Cheung, T.1
  • 7
    • 0020894692 scopus 로고
    • The performance of multistage interconnection networks for multiprocessors
    • C.P. Kruskal, "The performance of multistage interconnection networks for multiprocessors", IEEE Transactions on Computers 37 (11)(1986), pp1091-1098.
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    • Kruskal, C.P.1
  • 8
    • 0034276274 scopus 로고    scopus 로고
    • Tolerating Multiple faults in Multistage interconnection Networks with Minimal Extra Stages
    • C.C. Fan, J. Bruck, "Tolerating Multiple faults in Multistage interconnection Networks with Minimal Extra Stages", IEEE Transactions on Computers 49 (9) (2000), pp998-1004.
    • (2000) IEEE Transactions on Computers , vol.49 , Issue.9 , pp. 998-1004
    • Fan, C.C.1    Bruck, J.2
  • 9
    • 51849160034 scopus 로고    scopus 로고
    • D. Tutsch, M. Brenner, MINSimulate A Multistage Interconnection Network Simulator,. In 17th European Simulation Multiconference: Foundations for Successful Modeling & Simulation (ESM'03), Nottingham, pp 211.216.
    • D. Tutsch, M. Brenner, "MINSimulate A Multistage Interconnection Network Simulator",. In 17th European Simulation Multiconference: Foundations for Successful Modeling & Simulation (ESM'03), Nottingham, pp 211.216.
  • 11
    • 0036200627 scopus 로고    scopus 로고
    • Generating Systems of Equations for Performance Evaluation of Buffered Multistage Interconnection Networks
    • D. Tutsch, G. Hommel, "Generating Systems of Equations for Performance Evaluation of Buffered Multistage Interconnection Networks", Journal of Parallel and Distributed Computing 62 (2) (2002), pp228-240.
    • (2002) Journal of Parallel and Distributed Computing , vol.62 , Issue.2 , pp. 228-240
    • Tutsch, D.1    Hommel, G.2
  • 12
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    • On the universality of multistage interconnection networks
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  • 13
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    • A unified theory of interconnection network
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  • 14
    • 0036767571 scopus 로고    scopus 로고
    • A systematic analysis of Equivalence in Multistage Networks
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    • Collier, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.