-
1
-
-
0036859776
-
Multi-processor SoC platforms: A component-based design approach
-
W.O. Cesario, "Multi-processor SoC platforms: a component-based design approach", IEEE Design and Test of Computers 19 (6) (2002), pp52-63.
-
(2002)
IEEE Design and Test of Computers
, vol.19
, Issue.6
, pp. 52-63
-
-
Cesario, W.O.1
-
2
-
-
0029218595
-
The SP2 High-Performance Switch
-
C. Stunkel, "The SP2 High-Performance Switch", IBM Systems Journal 34 (2) (1995), pp. 185-204.
-
(1995)
IBM Systems Journal
, vol.34
, Issue.2
, pp. 185-204
-
-
Stunkel, C.1
-
4
-
-
79955143971
-
Creating a world of smart reconfigurable devices
-
R. Lauwereins, "Creating a world of smart reconfigurable devices", In Field Programmable Logic FPL (2002), pp790-794.
-
(2002)
In Field Programmable Logic FPL
, pp. 790-794
-
-
Lauwereins, R.1
-
5
-
-
0022752120
-
A simulation study of the cray x-mp memory system
-
T. Cheung, "A simulation study of the cray x-mp memory system", IEEE Transactions on Computers 35 (7) (1986), pp613-622.
-
(1986)
IEEE Transactions on Computers
, vol.35
, Issue.7
, pp. 613-622
-
-
Cheung, T.1
-
6
-
-
77955711630
-
MpNOC Design: Modeling and simulation
-
S. Duquennoy, S. Le Beux , P. Marquet , S. Meftali , J. Dekeyser, "MpNOC Design: modeling and simulation", In 15th IP based SOC Design Conference (2006), pp229-232.
-
(2006)
15th IP based SOC Design Conference
, pp. 229-232
-
-
Duquennoy, S.1
Le Beux, S.2
Marquet, P.3
Meftali, S.4
Dekeyser, J.5
-
7
-
-
0020894692
-
The performance of multistage interconnection networks for multiprocessors
-
C.P. Kruskal, "The performance of multistage interconnection networks for multiprocessors", IEEE Transactions on Computers 37 (11)(1986), pp1091-1098.
-
(1986)
IEEE Transactions on Computers
, vol.37
, Issue.11
, pp. 1091-1098
-
-
Kruskal, C.P.1
-
8
-
-
0034276274
-
Tolerating Multiple faults in Multistage interconnection Networks with Minimal Extra Stages
-
C.C. Fan, J. Bruck, "Tolerating Multiple faults in Multistage interconnection Networks with Minimal Extra Stages", IEEE Transactions on Computers 49 (9) (2000), pp998-1004.
-
(2000)
IEEE Transactions on Computers
, vol.49
, Issue.9
, pp. 998-1004
-
-
Fan, C.C.1
Bruck, J.2
-
9
-
-
51849160034
-
-
D. Tutsch, M. Brenner, MINSimulate A Multistage Interconnection Network Simulator,. In 17th European Simulation Multiconference: Foundations for Successful Modeling & Simulation (ESM'03), Nottingham, pp 211.216.
-
D. Tutsch, M. Brenner, "MINSimulate A Multistage Interconnection Network Simulator",. In 17th European Simulation Multiconference: Foundations for Successful Modeling & Simulation (ESM'03), Nottingham, pp 211.216.
-
-
-
-
11
-
-
0036200627
-
Generating Systems of Equations for Performance Evaluation of Buffered Multistage Interconnection Networks
-
D. Tutsch, G. Hommel, "Generating Systems of Equations for Performance Evaluation of Buffered Multistage Interconnection Networks", Journal of Parallel and Distributed Computing 62 (2) (2002), pp228-240.
-
(2002)
Journal of Parallel and Distributed Computing
, vol.62
, Issue.2
, pp. 228-240
-
-
Tutsch, D.1
Hommel, G.2
-
12
-
-
3042625073
-
On the universality of multistage interconnection networks
-
T. Szymanski, V. Hamacher, " On the universality of multistage interconnection networks", IEEE Computer Society Press (1994) , pp. 73-101.
-
(1994)
IEEE Computer Society Press
, pp. 73-101
-
-
Szymanski, T.1
Hamacher, V.2
-
13
-
-
0022952770
-
A unified theory of interconnection network
-
C Kruskal, M. Snir, "A unified theory of interconnection network ", Theoretical Computer Science 48 (1986), pp75-94.
-
(1986)
Theoretical Computer Science
, vol.48
, pp. 75-94
-
-
Kruskal, C.1
Snir, M.2
-
14
-
-
0036767571
-
A systematic analysis of Equivalence in Multistage Networks
-
M. Collier, "A systematic analysis of Equivalence in Multistage Networks", In Journal of Light wave Technology 20 (9) (2002), pp228-240.
-
(2002)
Journal of Light wave Technology
, vol.20
, Issue.9
, pp. 228-240
-
-
Collier, M.1
|