Trustworthy system security through 3-D integrated hardware

2008 IEEE International Workshop on Hardware-Oriented Security and Trust, HOST

Volumn , Issue , 2008, Pages 91-92

  Huffmire, Ted ^a   Valamehr, Jonathan ^b   Sherwood, Timothy ^b   Kastner, Ryan ^c   Levin, Timothy ^a   Nguyen, Thuy D ^a   Irvine, Cynthia ^a  

^a Naval Postgraduate School   (United States)

^b University of California   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 51849090209     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HST.2008.4559061     Document Type: Conference Paper

References (6)

1. Ziptronix, "3D integration for mixed signal applications," Morisville, NC, 2002. [Online]. Available: http://www.ziptronix.com/images/pdf/ analog_applications.pdf
2. F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir, "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory," Proceedings of the 33rd annual International Symposium on Computer Architecture (ISCA), pp. 130-141, July 2006.
3. B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCauley, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, and C. Webb, "Die Stacking (3D) Microarchitecture," Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 469-479, December 2006.
4. K. Puttaswamy and G. H. Loh, "Thermal analysis of a 3D diestacked high-performance microprocessor," Proceedings of the 16th ACM Great Lakes symposium on VLSI, pp. 19-24, May 2006.
5. S. Mysore, B. Agrawal, S. Lin, N. Srivastava, K. Banerjee, and T. Sherwood, "Introspective 3-D chips," in Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, CA, October 2006.
6. _, "3-D integration for introspection," IEEE Micro, vol. 27, no. 1, January 2007.