A memory-reduced Log-MAP kernel for turbo decoder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1032-1035

  Tsai, Tsung Han ^a   Lin, Cheng Hung ^b   Wu, An Yeu ^b  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

3GPP STANDARD; CMOS PROCESS; COMPARISON RESULT; CORE AREA; DATA ACCESS; KERNEL DESIGN; LOG-MAP; MEMORY SIZE; MEMORY USAGE; PROPOSED ARCHITECTURES; PROTOTYPING; TURBO DECODERS; TURBO DECODING;

DECODING;

EID: 51749117434     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464767     Document Type: Conference Paper

References (7)

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2. J. P. Woodard, and L. Hanzo, "Comparative study of turbo decoding techniques: an overview," IEEE Trans. Vehicular Technology, vol. 49, pp. 2208 2233, Nov. 2000.
3. A. J. Viterbi, "An intuitive justification and simplified implementation of the MAP decoder for convolutional codes," IEEE J. Selected Area in Commun., vol. 16, pp. 260-264, Feb. 1998.
4. E. Boutillon, W. J. Gross, and P. G. Gulak, "VLSI architectures for the MAP algorithm," IEEE Trans. on Commun., vol. 51, pp. 175-185, Feb. 2003.
5. "Technical Specification Group Radio Access Network; Multiplexing and Channel Coding (FDD)," 3rd Generation Partnership Project, 3GPP Ts25.212 v5.1.0, 2002.
6. A. Raghupathy, and K. J. R. Liu, "A transformation for computational latency reduction in turbo-MAP decoding," in Proc. ISCAS '99,vol. 4, pp. 402 405, Jul 1999.
7. J. Dielissen, and J. Huisken, "State vector reduction for initialization of sliding windows MAP," in Proc. 2nd Int. Symp. Turbo Codes, pp. 387-390, Sept. 2000.